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1. 发明授权

US06902939B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06902939B2
公开(公告)日：2005-06-07
申请号：US10223643
申请日：2002-08-19
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L21/302 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/311 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L21/00
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

2. 发明授权

US06635528B2 Method of planarizing a conductive plug situated under a ferroelectric capacitor 有权
标题翻译：平面化位于铁电电容器下方的导电插塞的方法
公开(公告)号：US06635528B2
公开(公告)日：2003-10-21
申请号：US09741675
申请日：2000-12-19
申请人： Stephen R. Gilbert , Scott Summerfelt , Luigi Colombo
发明人： Stephen R. Gilbert , Scott Summerfelt , Luigi Colombo
IPC分类号： H01L2100
CPC分类号： H01L21/32139 , H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/7687 , H01L21/76877 , H01L27/11502 , H01L27/11507 , H01L28/55
摘要： An embodiment of the instant invention is a method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides, the method comprising the steps of: depositing a first conductive material (114 of FIG. 7d) on the top surface of the dielectric layer and in the opening in the dielectric layer to substantially fill the opening with the conductive material; removing the portion of the first conductive material located on the dielectric layer and removing a portion of the first conductive material located in the opening in the dielectric layer to recess (406 of FIG. 7d) the first conductive material below the top surface of the dielectric layer; depositing a second conductive material (704 of FIG. 7d) in the recess to form a substantially planar top surface substantially coplanar with the top surface of the dielectric layer; and forming a third conductive material (302 of FIG. 7d) on the second conductive material, at least one of the second conductive material and the third conductive material acting as a diffusion barrier to prevent oxidation of the first conductive material.
摘要翻译：本发明的一个实施例是一种在具有顶表面，底表面和开口具有侧面的电介质层的开口中制造平面导电通孔的方法，所述方法包括以下步骤：将第一导电材料（114 在电介质层的顶表面和电介质层的开口中，以基本上用导电材料填充开口; 去除位于电介质层上的第一导电材料的部分，并且去除位于电介质层中的开口中的第一导电材料的一部分以凹陷（图7d的406）第一导电材料在电介质顶表面下方层; 在凹槽中沉积第二导电材料（图7d的704）以形成与介电层的顶表面基本上共面的基本平坦的顶表面; 以及在所述第二导电材料上形成第三导电材料（图7d的302），所述第二导电材料和所述第三导电材料中的至少一个用作扩散阻挡层以防止所述第一导电材料的氧化。

3. 发明授权

US06635497B2 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing 有权
公开(公告)号：US06635497B2
公开(公告)日：2003-10-21
申请号：US10036714
申请日：2001-12-21
申请人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
发明人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
IPC分类号： H01L2100
CPC分类号： H01L21/02197 , H01L21/02271 , H01L21/31691 , H01L27/10811 , H01L28/55 , H01L28/75
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

4. 发明授权

US06441415B1 Ferroelectric and paraelectric thin film devices using dopants which eliminate ferroelectricity 有权
标题翻译：使用消除铁电性的掺杂剂的铁电和顺电薄膜器件
公开(公告)号：US06441415B1
公开(公告)日：2002-08-27
申请号：US09344580
申请日：1999-06-25
申请人： Theodore S. Moise , Stephen R. Gilbert , Charles D. E. Lakeman , Scott R. Summerfelt , Stacey A. Yamanaka
发明人： Theodore S. Moise , Stephen R. Gilbert , Charles D. E. Lakeman , Scott R. Summerfelt , Stacey A. Yamanaka
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： A method for simultaneously producing areas of paraelectric states and areas of ferroelectric states on a single thin film layer, thereby reducing the number of processing steps required to produce integrated chips containing both standard capacitors and non-volatile memory devices from the number of steps needed using the conventional approach. A device containing both ferroelectric capacitors and non-ferroelectric capacitors using a single thin film as the dielectric.
摘要翻译：一种用于在单个薄膜层上同时产生顺电状态区域和铁电态区域的方法，从而减少了从所需步骤所需的步骤产生包含标准电容器和非易失性存储器件的集成芯片所需的处理步骤的数量常规方法。使用单个薄膜作为电介质的包含铁电电容器和非铁电电容器的装置。

5. 发明授权

US07361599B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US07361599B2
公开(公告)日：2008-04-22
申请号：US11145663
申请日：2005-06-06
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L21/302
CPC分类号： H01L27/11502 , H01L21/31116 , H01L21/76895 , H01L27/10811 , H01L27/10814 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

6. 发明授权

US06806101B2 Ferroelectric capacitor plasma charging monitor 有权
标题翻译：铁电电容器等离子充电监视器
公开(公告)号：US06806101B2
公开(公告)日：2004-10-19
申请号：US10422332
申请日：2003-04-24
申请人： Shawming Ma , Guoqiang Xing , Stephen R. Gilbert
发明人： Shawming Ma , Guoqiang Xing , Stephen R. Gilbert
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L28/55
摘要： Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.
摘要翻译：公开了用于在半导体晶片处理期间检测等离子体充电的等离子体充电装置和方法。公开了具有铁电电容元件的充电监视器，其可以在处理感兴趣的步骤之前被预编程，然后随后被测量，以便确定等离子体相关的充电是否是中间处理步骤中的问题。

7. 发明授权

US06692976B1 Post-etch cleaning treatment 有权
标题翻译：蚀刻后清洗处理
公开(公告)号：US06692976B1
公开(公告)日：2004-02-17
申请号：US09650224
申请日：2000-08-31
申请人： Laura Wills Mirkarimi , Stephen R. Gilbert , Guoqiang Xing , Scott Summerfelt , Tomoyuki Sakoda , Ted Moise
发明人： Laura Wills Mirkarimi , Stephen R. Gilbert , Guoqiang Xing , Scott Summerfelt , Tomoyuki Sakoda , Ted Moise
IPC分类号： H01L21306
CPC分类号： H01L28/55 , H01L21/02052 , H01L21/0206 , H01L21/31111 , H01L21/32134 , H01L28/75
摘要： The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.
摘要翻译：本公开涉及用于诸如FeRAM的半导体器件的后蚀刻清洁处理。该处理包括提供包括氟化合物和氯化合物两者的蚀刻剂，以及在湿清洗工艺中将蚀刻剂施加到半导体器件。

8. 发明授权

US06686236B2 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing 有权
标题翻译：通过金属有机化学气相沉积或其他处理防止PZT形成期间IrOx的还原的方法
公开(公告)号：US06686236B2
公开(公告)日：2004-02-03
申请号：US10036827
申请日：2001-12-21
申请人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
发明人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
IPC分类号： H01L218242
CPC分类号： H01L21/02197 , C23C14/08 , H01L21/02271 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60 , H01L28/75
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括在形成电容器的铁电介质部分期间降低底部电极材料的减少。以上述方式，铁电电容器的耐疲劳性大幅度提高。

9. 发明授权

US06548343B1 Method of fabricating a ferroelectric memory cell 有权
标题翻译：制造铁电存储单元的方法
公开(公告)号：US06548343B1
公开(公告)日：2003-04-15
申请号：US09702985
申请日：2000-10-31
申请人： Scott R. Summerfelt , Theodore S. Moise , Guoqiang Xing , Luigi Colombo , Tomoyuki Sakoda , Stephen R. Gilbert , Alvin L. S. Loke , Shawming Ma , Rahim Kavari , Laura Wills-Mirkarimi , Jun Amano
发明人： Scott R. Summerfelt , Theodore S. Moise , Guoqiang Xing , Luigi Colombo , Tomoyuki Sakoda , Stephen R. Gilbert , Alvin L. S. Loke , Shawming Ma , Rahim Kavari , Laura Wills-Mirkarimi , Jun Amano
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.
摘要翻译：本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤形成阻挡层的步骤。

10. 发明授权

US06444542B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06444542B2
公开(公告)日：2002-09-03
申请号：US09826283
申请日：2001-04-03
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L2176
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

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