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1. 发明申请

US20080044957A1 WORK FUNCTION CONTROL OF METALS 有权
标题翻译：金属的工作功能控制
公开(公告)号：US20080044957A1
公开(公告)日：2008-02-21
申请号：US11870631
申请日：2007-10-11
申请人： James Chambers , Mark Visokay , Luigi Colombo , Antonio Rotondaro
发明人： James Chambers , Mark Visokay , Luigi Colombo , Antonio Rotondaro
IPC分类号： H01L21/84
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译：公开了具有不同功函数的金属栅极晶体管。在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

2. 发明申请

US20070122962A1 Semiconductor CMOS Devices and Methods with NMOS High-K Dielectric Present in Core Region that Mitigate Damage to Dielectric Materials 有权
标题翻译：半导体CMOS器件和方法与NMOS High-K介质存在于核心区域，减轻对介质材料的损害
公开(公告)号：US20070122962A1
公开(公告)日：2007-05-31
申请号：US11620447
申请日：2007-01-05
申请人： James Chambers , Mark Visokay , Luigi Colombo
发明人： James Chambers , Mark Visokay , Luigi Colombo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , Y10S438/981
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
摘要翻译：本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。在半导体器件（506）的芯和I / O区域中形成I / O电介质层。从器件的芯区域去除（508）I / O电介质层。在芯区域（510）中形成芯介质层。屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。从核心NMOS器件（514）去除芯介质层。在核心和I / O区域上形成高k电介质层（514）。然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

3. 发明申请

US20070037343A1 Process for manufacturing dual work function metal gates in a microelectronics device 有权
公开(公告)号：US20070037343A1
公开(公告)日：2007-02-15
申请号：US11200741
申请日：2005-08-10
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/66545
摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

4. 发明授权

US07037730B2 Capacitor with high dielectric constant materials and method of making 失效
标题翻译：具有高介电常数材料和制作方法的电容器
公开(公告)号：US07037730B2
公开(公告)日：2006-05-02
申请号：US09904112
申请日：2001-07-11
申请人： Cem Basceri , Gurtej S. Sandhu , Mark Visokay
发明人： Cem Basceri , Gurtej S. Sandhu , Mark Visokay
IPC分类号： H01L21/8242
CPC分类号： H01L28/56 , H01L27/10811
摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1−x)TiO3, and methods of making such capacitors and DRAM cells are provided. A preferred method includes providing a conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the conductive oxide electrode and the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.
摘要翻译：使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元）和提供制造这种电容器和DRAM单元的方法。优选的方法包括提供导电氧化物电极，在导电氧化物电极上沉积高介电常数氧化物介电材料的第一层，在氧化条件下氧化导电氧化物电极和高介电常数氧化物介电材料的第一层，沉积在所述电介质的第一层上的所述高介电常数氧化物电介质材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

5. 发明申请

US20060043524A1 Versatile system for triple-gated transistors with engineered corners 有权
公开(公告)号：US20060043524A1
公开(公告)日：2006-03-02
申请号：US11221103
申请日：2005-09-07
申请人： Mark Visokay , James Chambers
发明人： Mark Visokay , James Chambers
IPC分类号： H01L29/00
CPC分类号： H01L29/7831 , H01L29/66484
摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

6. 发明申请

US20050136589A1 Method for integrating high-k dielectrics in transistor devices 有权
标题翻译：在晶体管器件中集成高k电介质的方法
公开(公告)号：US20050136589A1
公开(公告)日：2005-06-23
申请号：US10738958
申请日：2003-12-17
申请人： Antonio Rotondaro , Douglas Mercer , Luigi Colombo , Mark Visokay , Haowen Bu , Malcolm Bevan
发明人： Antonio Rotondaro , Douglas Mercer , Luigi Colombo , Mark Visokay , Haowen Bu , Malcolm Bevan
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/51
CPC分类号： H01L21/28176 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.
摘要翻译：公开了制造具有高k电介质层的半导体器件的方法。本发明除了不在门下方的沉积的高k电介质层的部分，并且在用封装层制造期间覆盖高k电介质层的暴露部分（例如，侧壁），这减轻了高k电介质层中的缺陷和工艺污染工具封装层也可以用作蚀刻停止层，并且至少部分地包括侧壁间隔物。结果，可以制造具有基本均匀的等效氧化物厚度的半导体器件。

7. 发明申请

US20050124121A1 Anneal of high-k dielectric using NH3 and an oxidizer 审中-公开
标题翻译：使用NH3和氧化剂的高k电介质的退火
公开(公告)号：US20050124121A1
公开(公告)日：2005-06-09
申请号：US10731647
申请日：2003-12-09
申请人： Antonio Rotondaro , James Chambers , Mark Visokay , Luigi Colombo
发明人： Antonio Rotondaro , James Chambers , Mark Visokay , Luigi Colombo
IPC分类号： C23C16/56 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/4763 , H01L21/8242 , H01L29/51
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3143 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention pertains to annealing a high dielectric constant (high-k) material in a manner that substantially reduces or eliminates disadvantages and problems heretofore associated with the same. In particular, the high-k material is annealed in an ambient having a single chemistry of nitrogen and hydrogen, such as ammonia (NH3), to nitride and react unwanted impurities, and an oxidizer to oxidize and densify the high-k material, while mitigating growth of a lower-k material at an interface of the high-k material and an underlying substrate. Additionally, particular temperatures and pressures are utilized within the process so that the risk of an undesired exothermic reaction is mitigated. Annealing the high-k material in accordance with manners disclosed herein has application to semiconductor fabrication processes and, as such, is discussed herein within the context of the same.
摘要翻译：本发明涉及以大大减少或消除与之相关的缺点和问题的方式退火高介电常数（高k）材料。特别地，高k材料在具有氮和氢的单一化学性质（例如氨（NH 3））的环境中退火至氮化物并反应不需要的杂质，以及氧化剂氧化和致密化高k材料，同时减轻在高k材料和下层衬底的界面处的较低k材料的生长。此外，在该方法中利用特定的温度和压力，以便减轻不期望的放热反应的风险。根据本文公开的方式对高k材料进行退火，已经应用于半导体制造工艺，并且因此本文在其上下文中讨论。

8. 发明申请

US20050101145A1 Semiconductor structure and method of fabrication 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20050101145A1
公开(公告)日：2005-05-12
申请号：US10703388
申请日：2003-11-06
申请人： Mark Visokay , Luigi Colombo
发明人： Mark Visokay , Luigi Colombo
IPC分类号： H01L21/302 , H01L21/461 , H01L21/8238
CPC分类号： H01L21/823842
摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.
摘要翻译：制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。

9. 发明授权

US06833576B2 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 失效
标题翻译：含有钌和钨的层的形成方法和集成电路结构
公开(公告)号：US06833576B2
公开(公告)日：2004-12-21
申请号：US10002779
申请日：2001-10-29
申请人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.
摘要翻译：具有增加的电容的电容器包括增强的表面积（粗糙表面）导电层或与高介电常数材料相容的其它层。在一种方法中，用于这种电容器的增强表面积导电层是通过在高温或高于500℃，低压75托或更低，最理想的5托或更低的高温下处理氧化钌层形成的，产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。该层可以形成在下面的导电层上。处理可以在惰性环境或还原环境中进行。可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。氧化环境中的处理也可以进行以钝化粗糙层。可以使用粗糙化的钌层来形成增强表面积的导电层。所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。在另一种方法中，提供氮化钨层作为这种电容器的第一电极。电容器或至少氮化钨层被退火以增加电容器的电容。

10. 发明授权

US06740554B2 Methods to form rhodium-rich oxygen barriers 失效
标题翻译：形成富铑氧气屏障的方法
公开(公告)号：US06740554B2
公开(公告)日：2004-05-25
申请号：US10209386
申请日：2002-07-30
申请人： Haining Yang , Dan Gealy , Gurtej S. Sandhu , Howard Rhodes , Mark Visokay
发明人： Haining Yang , Dan Gealy , Gurtej S. Sandhu , Howard Rhodes , Mark Visokay
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： A structure and method are disclosed for forming a capacitor for an integrated circuit. The capacitor includes a rhodium-rich structure, a rhodium oxide layer in direct contact with the rhodium-rich structure, a capacitor dielectric in direct contact with the rhodium oxide layer and a top electrode over the capacitor. The rhodium-rich structure can include rhodium alloys and the capacitor dielectric preferably has a high dielectric constant.
摘要翻译：公开了一种用于形成用于集成电路的电容器的结构和方法。电容器包括富铑结构，与富铑结构直接接触的铑氧化物层，与氧化铑层直接接触的电容器电介质和电容器上的顶电极。富铑结构可以包括铑合金，并且电容器电介质优选具有高的介电常数。

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