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    • 3. 发明申请
    • Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories
    • 2T2C铁电存储器的交错位线架构
    • US20120307545A1
    • 2012-12-06
    • US13150885
    • 2011-06-01
    • Hugh P. McAdamsScott R. SummerfeltPatrick M. Ndai
    • Hugh P. McAdamsScott R. SummerfeltPatrick M. Ndai
    • G11C11/22
    • G11C11/221
    • A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.
    • 具有双晶体管,双电容器(2T2C)型的交错成对的铁电存储器单元的铁电存储器。 给定对中的每个存储单元被构造为第一和第二部分,每个部分包括晶体管和铁电电容器。 在每对内,第二存储单元的第一部分物理地位于第一存储单元的第一和第二部分之间。 结果,用于相邻列的互补位线彼此交错。 每个读出放大器与复用器相关联,使得交错存储器单元的相邻列由单个读出放大器支持。 位线之间的噪声耦合减少,并且读出放大器可以沿着阵列的一侧放置,减少了消除边缘单元效应所需的虚拟单元的数量。
    • 4. 发明授权
    • Alignment mark for opaque layer
    • 不透明层的对齐标记
    • US08324742B2
    • 2012-12-04
    • US12185003
    • 2008-08-01
    • Scott R. SummerfeltStephen A. MeisnerJohn B. Robbins
    • Scott R. SummerfeltStephen A. MeisnerJohn B. Robbins
    • H01L23/544H01L21/76
    • H01L23/544H01L2223/54426H01L2223/54453H01L2223/5448H01L2924/0002H01L2924/00
    • An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.
    • 公开了在不透明层下使用的接触金属层中的IC对准标记和用于形成对准标记的工艺。 对准标记包括几微米宽的接触金属场,在接触蚀刻期间形成的PMD柱阵列,接触金属沉积和选择性接触金属去除过程。 柱子被排列成使得接触金属的所有暴露表面是平面的。 一个配置是矩形阵列,其中每隔一行被横向偏移列间距的一半。 选择柱的水平尺寸以使接触金属填充因子最大化,同时在处理期间向下面的基底提供足够的粘附。 作为接触金属去除过程的结果,接触金属比围绕对准标记的PMD层低至少15纳米。
    • 9. 发明申请
    • Increasing Exposure Tool Alignment Signal Strength for a Ferroelectric Capacitor Layer
    • 增加铁电电容层的曝光工具对准信号强度
    • US20110014360A1
    • 2011-01-20
    • US12889851
    • 2010-09-24
    • Stephen Arion MeisnerScott R. Summerfelt
    • Stephen Arion MeisnerScott R. Summerfelt
    • H05K3/00
    • H01L23/544G03F9/7076G03F9/7084H01L2223/54453H01L2924/0002Y10T29/42H01L2924/00
    • An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.
    • 公开了用于光刻图案对准的改进的对准结构。 在低反射率层下的IC中的地形对准标记可能难以注册。 在低反射层的顶部形成反射层,使得对准标记的形貌在反射层中复制,使得能够使用普通的光刻扫描器和步进器对准对准标记。 反射层可以是一个或多个层,并且可以是金属的,电介质的或两者的。 反射层可以在整个IC上是全局的,或者可以是对准标记区域的局部。 可以在随后的处理期间去除反射层,可能来自添加的蚀刻停止层的辅助,或者可以保留在完整的IC中。 所公开的对准标记结构可应用于具有堆叠铁电电容器材料的IC。