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1. 发明授权

US07129162B2 Dual cap layer in damascene interconnection processes 有权
标题翻译：大马士革互连工艺中的双盖层
公开(公告)号：US07129162B2
公开(公告)日：2006-10-31
申请号：US10429119
申请日：2003-05-02
申请人： Hyesook Hong , Guoqiang Xing , Ping Jiang
发明人： Hyesook Hong , Guoqiang Xing , Ping Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76802 , H01L21/76808
摘要： Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.
摘要翻译：公开了用于形成铜导体（30,130）的镶嵌方法。根据所公开的方法，在将通孔或沟槽蚀刻到下面的导体（12;）之前，在有机硅酸盐玻璃绝缘层（16; 116,120）上形成双重覆盖层（18,20; 122,124）。 112）。双盖层包括碳化硅层（18; 124）和氮化硅层（20; 122）。碳化硅层（18; 124）和氮化硅层（20; 122）可以以相对于彼此的任何顺序沉积。碳化硅层（18; 124）在蚀刻通过绝缘层（16; 116,120）时保持通孔或沟槽的临界尺寸，而氮化硅层（20; 122）抑制抗蚀剂的失效机理中毒该方法适用于单镶嵌工艺，但也可用于双镶嵌铜工艺。

2. 发明授权

US06902939B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06902939B2
公开(公告)日：2005-06-07
申请号：US10223643
申请日：2002-08-19
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L21/302 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/311 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L21/00
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

3. 发明授权

US06485988B2 Hydrogen-free contact etch for ferroelectric capacitor formation 有权
标题翻译：用于铁电电容器形成的无氢接触蚀刻
公开(公告)号：US06485988B2
公开(公告)日：2002-11-26
申请号：US09741650
申请日：2000-12-19
申请人： Shawming Ma , Guoqiang Xing , Rahim Kavari , Scott R. Summerfelt , Tomoyuki Sakoda
发明人： Shawming Ma , Guoqiang Xing , Rahim Kavari , Scott R. Summerfelt , Tomoyuki Sakoda
IPC分类号： H01L2100
CPC分类号： H01L21/31122 , H01L21/32136 , H01L21/76838 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/60
摘要： An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.
摘要翻译：本发明的一个实施方案是一种形成导电接触的方法，该导电接触由位于顶部电极下方的底部电极（图4d的304）构成的铁电电容器的顶部电极（图4d的308和310）和铁电材料（图4d的306）位于顶部电极和底部电极之间，该方法包括以下步骤：在顶部电极上形成层（图4的408或312）; 在所述层中形成开口（图4d的414），以通过使用无氢蚀刻剂将所述开口蚀刻到所述层中来暴露所述顶部电极的一部分; 以及将导电材料（图4d的432）沉积在开口中以与顶部电极形成电连接。

4. 发明授权

US06410426B1 Damascene cap layer process for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的镶嵌帽层工艺
公开(公告)号：US06410426B1
公开(公告)日：2002-06-25
申请号：US09901392
申请日：2001-07-09
申请人： Guoqiang Xing , Ping Jiang
发明人： Guoqiang Xing , Ping Jiang
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76802 , Y10S438/97
摘要： The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).
摘要翻译：本发明描述了一种用于形成集成电路互连的方法。在低k电介质层（40）上形成覆盖层（50）。蚀刻覆盖层（50）和低k电介质层（40）以在填充有导电材料（90）（95）的低k电介质（4）中形成通孔和/或沟槽。

5. 发明授权

US07361599B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US07361599B2
公开(公告)日：2008-04-22
申请号：US11145663
申请日：2005-06-06
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L21/302
CPC分类号： H01L27/11502 , H01L21/31116 , H01L21/76895 , H01L27/10811 , H01L27/10814 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

6. 发明授权

US06872665B1 Process flow for dual damescene interconnect structures 有权
标题翻译：双重二连体互连结构的工艺流程
公开(公告)号：US06872665B1
公开(公告)日：2005-03-29
申请号：US09599718
申请日：2000-06-22
申请人： Francis G. Celii , Guoqiang Xing , Andrew McKerrow , Andrew Ralston , Zhicheng Tang , Kenneth J. Newton , Robert Kraft , Jeff West
发明人： Francis G. Celii , Guoqiang Xing , Andrew McKerrow , Andrew Ralston , Zhicheng Tang , Kenneth J. Newton , Robert Kraft , Jeff West
IPC分类号： H01L21/768 , H01L21/20
CPC分类号： H01L21/76808
摘要： A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.
摘要翻译：用于形成互连线和通孔的双镶嵌工艺流程，其中在沟槽蚀刻之前蚀刻至少部分通孔（116）。使用低k材料如热固性有机聚合物用于ILD（106）和IMD（110）。在至少部分通孔蚀刻之后，BARC（120）沉积在包括在通孔（116）中的结构上。然后，对沟槽（126）进行图案化和蚀刻。虽然在沟槽蚀刻期间去除了至少一些BARC（120）材料，但是通孔（116）的底部被保护。

7. 发明授权

US06806101B2 Ferroelectric capacitor plasma charging monitor 有权
标题翻译：铁电电容器等离子充电监视器
公开(公告)号：US06806101B2
公开(公告)日：2004-10-19
申请号：US10422332
申请日：2003-04-24
申请人： Shawming Ma , Guoqiang Xing , Stephen R. Gilbert
发明人： Shawming Ma , Guoqiang Xing , Stephen R. Gilbert
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L28/55
摘要： Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.
摘要翻译：公开了用于在半导体晶片处理期间检测等离子体充电的等离子体充电装置和方法。公开了具有铁电电容元件的充电监视器，其可以在处理感兴趣的步骤之前被预编程，然后随后被测量，以便确定等离子体相关的充电是否是中间处理步骤中的问题。

8. 发明授权

US06692976B1 Post-etch cleaning treatment 有权
标题翻译：蚀刻后清洗处理
公开(公告)号：US06692976B1
公开(公告)日：2004-02-17
申请号：US09650224
申请日：2000-08-31
申请人： Laura Wills Mirkarimi , Stephen R. Gilbert , Guoqiang Xing , Scott Summerfelt , Tomoyuki Sakoda , Ted Moise
发明人： Laura Wills Mirkarimi , Stephen R. Gilbert , Guoqiang Xing , Scott Summerfelt , Tomoyuki Sakoda , Ted Moise
IPC分类号： H01L21306
CPC分类号： H01L28/55 , H01L21/02052 , H01L21/0206 , H01L21/31111 , H01L21/32134 , H01L28/75
摘要： The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.
摘要翻译：本公开涉及用于诸如FeRAM的半导体器件的后蚀刻清洁处理。该处理包括提供包括氟化合物和氯化合物两者的蚀刻剂，以及在湿清洗工艺中将蚀刻剂施加到半导体器件。

9. 发明授权

US06635498B2 Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch 有权
标题翻译：在底部电极蚀刻期间用侧壁构图FeRAM电容器的方法
公开(公告)号：US06635498B2
公开(公告)日：2003-10-21
申请号：US10222718
申请日：2002-08-16
申请人： Scott R. Summerfelt , Guoqiang Xing , Luigi Colombo , Sanjeev Aggarwal , Theodore S. Moise, IV
发明人： Scott R. Summerfelt , Guoqiang Xing , Luigi Colombo , Sanjeev Aggarwal , Theodore S. Moise, IV
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/31122 , H01L21/32136 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。

10. 发明授权

US06548343B1 Method of fabricating a ferroelectric memory cell 有权
标题翻译：制造铁电存储单元的方法
公开(公告)号：US06548343B1
公开(公告)日：2003-04-15
申请号：US09702985
申请日：2000-10-31
申请人： Scott R. Summerfelt , Theodore S. Moise , Guoqiang Xing , Luigi Colombo , Tomoyuki Sakoda , Stephen R. Gilbert , Alvin L. S. Loke , Shawming Ma , Rahim Kavari , Laura Wills-Mirkarimi , Jun Amano
发明人： Scott R. Summerfelt , Theodore S. Moise , Guoqiang Xing , Luigi Colombo , Tomoyuki Sakoda , Stephen R. Gilbert , Alvin L. S. Loke , Shawming Ma , Rahim Kavari , Laura Wills-Mirkarimi , Jun Amano
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.
摘要翻译：本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤形成阻挡层的步骤。

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