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    • 1. 发明授权
    • Dual cap layer in damascene interconnection processes
    • 大马士革互连工艺中的双盖层
    • US07129162B2
    • 2006-10-31
    • US10429119
    • 2003-05-02
    • Hyesook HongGuoqiang XingPing Jiang
    • Hyesook HongGuoqiang XingPing Jiang
    • H01L21/4763
    • H01L21/76832H01L21/76801H01L21/76802H01L21/76808
    • Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.
    • 公开了用于形成铜导体(30,130)的镶嵌方法。 根据所公开的方法,在将通孔或沟槽蚀刻到下面的导体(12;)之前,在有机硅酸盐玻璃绝缘层(16; 116,120)上形成双重覆盖层(18,20; 122,124)。 112)。 双盖层包括碳化硅层(18; 124)和氮化硅层(20; 122)。 碳化硅层(18; 124)和氮化硅层(20; 122)可以以相对于彼此的任何顺序沉积。 碳化硅层(18; 124)在蚀刻通过绝缘层(16; 116,120)时保持通孔或沟槽的临界尺寸,而氮化硅层(20; 122)抑制抗蚀剂的失效机理 中毒 该方法适用于单镶嵌工艺,但也可用于双镶嵌铜工艺。
    • 4. 发明授权
    • Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
    • 用于形成单镶嵌通孔或沟槽的方法以及通过空腔形成双镶嵌
    • US07214609B2
    • 2007-05-08
    • US10313491
    • 2002-12-05
    • Ping JiangRob KraftGuoqiang XingKaren H. R. KirmseEden Zielinski
    • Ping JiangRob KraftGuoqiang XingKaren H. R. KirmseEden Zielinski
    • H01L21/44H01L21/4763
    • H01L21/76808H01L21/76802
    • Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.
    • 公开了用于在单个镶嵌互连结构中形成沟槽或通孔腔的方法,包括蚀刻介电层以在其中形成空腔并暴露下面的蚀刻停止层,以及蚀刻暴露的蚀刻停止层以延伸空腔,并且 暴露现有互连结构中的导电特征,其中蚀刻介电层的一部分并蚀刻蚀刻停止层的暴露部分同时进行,其间基本上没有中间处理步骤。 还公开了在双镶嵌互连结构中形成通孔腔的方法,包括在现有互连结构上形成蚀刻停止层,在蚀刻停止层上形成电介质层,蚀刻介电层的一部分以形成 并且暴露蚀刻停止层的一部分,以及蚀刻蚀刻停止层以延伸通孔腔,其中介电层在蚀刻停止层的蚀刻期间被覆盖。
    • 8. 发明授权
    • Method of dry etching PZT capacitor stack to form high-density ferroelectric memory devices
    • US06492222B1
    • 2002-12-10
    • US09739065
    • 2000-12-18
    • Guoqiang Xing
    • Guoqiang Xing
    • H01L218242
    • H01L27/11502G11C11/22H01L21/31122H01L27/11507H01L28/55
    • An embodiment of the instant invention is a method of fabricating a ferroelectric memory device (125 of FIG. 1) comprised of a top electrode (128 and 130 of FIG. 1) over a bottom electrode (124 of FIG. 1) with a ferroelectric material (126 of FIG. 1) located between the top electrode and the bottom electrode, the method comprising the steps of: providing a stack including: a layer of bottom electrode material, a layer of top electrode material, and a layer of ferroelectric material situated between the layer of bottom electrode material and the top electrode material; depositing a layer of hardmask material on the layer of top electrode material, the hardmask material being comprised of a refractory nitride; removing a portion of the layer of hardmask material thereby exposing a portion of the layer of top electrode material by subjecting the portion of the layer of hardmask material to a first gas comprised of a first chlorine-bearing species and argon; removing the exposed portion of the layer of top electrode material thereby exposing a portion of the layer of ferroelectric material by subjecting the exposed portion of the layer of top electrode material to a second gas comprised of nitrogen, a first oxygen-bearing species, argon, and a second chlorine-bearing species; removing the exposed portion of the layer of ferroelectric material thereby exposing a portion of the layer of bottom electrode material by subjecting the exposed portion of the ferroelectric material to a third gas comprised of a third chlorine-bearing species, a second oxygen-bearing species, and a first fluorine-bearing species; and removing the exposed portion of the layer of bottom electrode material by subjecting the exposed portion of the layer of bottom electrode material to a fourth gas comprised of nitrogen, argon, a fourth chlorine-bearing species, and a third oxygen-bearing species.