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1. 发明授权

US06194313B1 Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process 失效
标题翻译：用于减少用于形成用于回蚀工艺的局部互连和/或插塞沟槽填充的凹部的方法
公开(公告)号：US06194313B1
公开(公告)日：2001-02-27
申请号：US09060971
申请日：1998-04-15
申请人： Abha R. Singh , Girish Anant Dixit , Wei-Yung Hsu , Guoqiang Xing
发明人： Abha R. Singh , Girish Anant Dixit , Wei-Yung Hsu , Guoqiang Xing
IPC分类号： H01L2144
CPC分类号： H01L21/76819 , H01L21/7684 , H01L21/76895
摘要： A method to reduce the effective recess in conductive plugs 220 by performing an oxide etch or oxide CMP, selective to the conductive material in question. This method can be used for any conductive plug 220 (e.g. aluminum, tungsten, copper, titanium nitride, etc.). In addition, this method is also applicable in contact, via, and trench (damascene) applications. Furthermore, this process can advantageously be used in logic, SRAM, and DRAM applications.
摘要翻译：通过对所讨论的导电材料进行选择性的氧化物蚀刻或氧化物CMP来减小导电插塞220中的有效凹部的方法。该方法可用于任何导电插头220（例如铝，钨，铜，氮化钛等）。此外，该方法也适用于接触，通孔和沟槽（镶嵌）应用。此外，该过程可以有利地用于逻辑，SRAM和DRAM应用中。

2. 发明授权

US5960311A Method for forming controlled voids in interlevel dielectric 失效
标题翻译：在层间电介质中形成受控空隙的方法
公开(公告)号：US5960311A
公开(公告)日：1999-09-28
申请号：US911291
申请日：1997-08-14
申请人： Abha R. Singh , Artur P. Balasinski , Ming M. Li
发明人： Abha R. Singh , Artur P. Balasinski , Ming M. Li
IPC分类号： H01L21/31 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/469
CPC分类号： H01L21/76819 , H01L21/31 , H01L21/76801 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002
摘要： A method of forming a thick interlevel dielectric layer containing sealed voids, formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings. An etchback may be chosen so that all voids are exposed. The exposed voids are filled with a flowable dielectric which can be then etched back to leave the flowable dielectric in the exposed voids. A second conformal interlevel dielectric layer is formed over the first conformal interlevel dielectric to further bury the sealed voids, insuring that they do not get exposed in further process steps. The second conformal interlevel dielectric may be formed in a thin layer to allow the flowable dielectric to remain near the top of the interlevel dielectric structure to reduce the possibility of poisoned vias.
摘要翻译：在半导体器件结构中，在基本平坦的表面上形成包含以受控方式形成的密封空隙的厚层间电介质层的方法以及根据这种方法形成的半导体结构。密封的空隙用于降低层间电容。在全局平坦化的绝缘体上形成多个金属信号线。在金属信号线上方以及在金属信号线之间形成的金属间间隔之间沉积厚层的第一共形层间电介质。由于层间电介质的厚度，流动特性和沉积方式以及金属间距的纵横比，在第一共形层间电介质中，在金属间距内形成空隙。然后将该层间电介质蚀刻或抛光回到期望的厚度，其在更宽的金属间距中暴露空隙，但不会在较窄的金属间间隔中暴露空隙。可以选择回蚀，使得所有空隙都被暴露。暴露的空隙填充有可流动的电介质，然后可以将其电蚀回去以使暴露的空隙中的可流动电介质留下。在第一共形层间电介质上形成第二共形层间电介质层，以进一步掩埋密封的空隙，确保它们不会在进一步的工艺步骤中暴露。第二共形层间电介质可以形成在薄层中，以允许可流动电介质保持在层间电介质结构的顶部附近，以减少中毒过孔的可能性。

3. 发明授权

US5736433A Double mask hermetic passivation method providing enhanced resistance to moisture 失效
标题翻译：双面罩密封钝化方法提供增强的耐湿性
公开(公告)号：US5736433A
公开(公告)日：1998-04-07
申请号：US778021
申请日：1996-12-31
申请人： Frank R. Bryant , Abha R. Singh , James A. Cunningham
发明人： Frank R. Bryant , Abha R. Singh , James A. Cunningham
IPC分类号： H01L21/316 , H01L21/66 , H01L21/70 , H01L21/82 , H01L23/31 , H01L23/50
CPC分类号： H01L23/3171 , H01L22/22 , H01L22/14 , H01L2924/0002
摘要： A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging. The second passivation layer overlaps edge portions of the first passivation layer at the bond pads to enhance moisture resistance.
摘要翻译：使用两个钝化层和使用两个掩蔽步骤的保护性外涂层形成钝化结构。第一钝化层形成在晶片之上，并且提供开口以暴露焊盘的部分以测试设备和可熔链路。在测试和激光修复之后，在晶片上形成第二钝化层，然后沉积保护外涂层。保护性外涂层被图案化和蚀刻，露出垫。保护性外涂层的其余部分用作掩模以去除覆盖在焊盘上的第二钝化层的部分。引线然后连接到焊盘，并且器件被封装以进行封装。第二钝化层在接合焊盘处与第一钝化层的边缘部分重叠以增强耐湿性。

4. 发明授权

US5847464A Method for forming controlled voids in interlevel dielectric 失效
标题翻译：在层间电介质中形成受控空隙的方法
公开(公告)号：US5847464A
公开(公告)日：1998-12-08
申请号：US534669
申请日：1995-09-27
申请人： Abha R. Singh , Artur P. Balasinski , Ming M. Li
发明人： Abha R. Singh , Artur P. Balasinski , Ming M. Li
IPC分类号： H01L21/31 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76819 , H01L21/31 , H01L21/76801 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002
摘要： A method of forming a thick interlevel dielectric layer containing sealed voids formed in a controlled manner, over a substantially planar surface in semiconductor device structure, and the semiconductor structure formed according to such a method. The sealed voids are used to reduce interlevel capacitance. A plurality of metal signal lines are formed over a globally planarized insulator. A thick layer of first conformal interlevel dielectric is deposited over the metal signal lines and over the intermetal spacings formed between the metal signal lines. Because of the thickness, flow properties, and manner of deposition of the interlevel dielectric and the aspect ratio the intermetal spacings, voids are formed in the first conformal interlevel dielectric, in the intermetal spacings. This interlevel dielectric is then etched or polished back to the desired thickness, which exposes the voids in the wider intermetal spacings, but does not expose voids in the narrower intermetal spacings. An etchback may be chosen so that all voids are exposed. The exposed voids are filled with a flowable dielectric which can be then etched back to leave the flowable dielectric in the exposed voids. A second conformal interlevel dielectric layer is formed over the first conformal interlevel dielectric to further bury the sealed voids, insuring that they do not get exposed in further process steps. The second conformal interlevel dielectric may be formed in a thin layer to allow the flowable dielectric to remain near the top of the interlevel dielectric structure to reduce the possibility of poisoned vias.
摘要翻译：在半导体器件结构中的基本上平坦的表面上形成以受控方式形成的密封空隙的厚层间电介质层的方法以及根据这种方法形成的半导体结构。密封的空隙用于降低层间电容。在全局平坦化的绝缘体上形成多个金属信号线。在金属信号线上方以及在金属信号线之间形成的金属间间隔之间沉积厚层的第一共形层间电介质。由于层间电介质的厚度，流动特性和沉积方式以及金属间距的纵横比，在第一共形层间电介质中，在金属间距内形成空隙。然后将该层间电介质蚀刻或抛光回到期望的厚度，其在更宽的金属间距中暴露空隙，但不会在较窄的金属间间隔中暴露空隙。可以选择回蚀，使得所有空隙都被暴露。暴露的空隙填充有可流动的电介质，然后可以将其电蚀回去以使暴露的空隙中的可流动电介质留下。在第一共形层间电介质上形成第二共形层间电介质层，以进一步掩埋密封的空隙，确保它们不会在进一步的工艺步骤中暴露。第二共形层间电介质可以形成在薄层中，以允许可流动电介质保持在层间电介质结构的顶部附近，以减少中毒过孔的可能性。

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