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1. 发明授权

US06323095B1 Method for reducing junction capacitance using a halo implant photomask 有权
标题翻译：使用光晕植入光掩模降低结电容的方法
公开(公告)号：US06323095B1
公开(公告)日：2001-11-27
申请号：US09489178
申请日：2000-01-21
申请人： Mark W. Michael , Jon D. Cheek , Robert Dawson
发明人： Mark W. Michael , Jon D. Cheek , Robert Dawson
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/266 , H01L21/8238 , H01L29/1083
摘要： A method for forming a semiconductor device is provided. The method includes providing a substrate having a gate formed thereon. A first doped region is formed in the substrate. The first doped region extends a first distance from the gate. A second doped region is formed in the substrate. The second doped region extends a second distance from the gate. The first distance is less than the second distance. A semiconductor device includes a substrate, isolation structures defined in the substrate, and a gate disposed on the substrate between adjacent isolation structures. A first doped region is defined in the substrate proximate the gate. The first doped region extends a first distance from the gate. A second doped region is defined in the substrate proximate the gate. The second doped region extends a second distance from the gate. The first distance is less than the first distance.
摘要翻译：提供一种形成半导体器件的方法。该方法包括提供其上形成有栅极的基板。在衬底中形成第一掺杂区。第一掺杂区域从栅极延伸第一距离。在衬底中形成第二掺杂区。第二掺杂区域从栅极延伸第二距离。第一距离小于第二距离。半导体器件包括衬底，限定在衬底中的隔离结构以及设置在相邻隔离结构之间的衬底上的栅极。在靠近栅极的衬底中限定第一掺杂区域。第一掺杂区域从栅极延伸第一距离。在靠近栅极的衬底中限定第二掺杂区域。第二掺杂区域从栅极延伸第二距离。第一距离小于第一距离。

2. 发明授权

US06261885B1 Method for forming integrated circuit gate conductors from dual layers of polysilicon 有权
标题翻译：从双层多晶硅形成集成电路栅极导体的方法
公开(公告)号：US06261885B1
公开(公告)日：2001-07-17
申请号：US09497789
申请日：2000-02-03
申请人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
发明人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
IPC分类号： H01L218238
CPC分类号： H01L21/82345
摘要： A method for fabricating an integrated circuit is presented wherein a first polysilicon layer dielectrically spaced above a semiconductor substrate is provided. The semiconductor substrate contains a first active region and a second active region. A first dopant is selectively introduced into the portion of the first polysilicon layer above the second active region. A second polysilicon layer may then be formed upon the first polysilicon layer and above the first active region and the second active region. A second dopant may be selectively introduced into a portion of the second polysilicon layer above the first active region. The portion of the second polysilicon layer above the first active region and the portion of the first polysilicon layer above the first active region may be patterned to form a first gate structure within the first active region. The portion of the second polysilicon layer above the second active region and the portion of the first polysilicon layer above the second active region may be patterned to form a second gate structure within the second active region.
摘要翻译：提出了一种用于制造集成电路的方法，其中提供介于半导体衬底之上的第一多晶硅层。半导体衬底包含第一有源区和第二有源区。第一掺杂剂被选择性地引入第二有源区上方的第一多晶硅层的部分。然后可以在第一多晶硅层上并且在第一有源区和第二有源区上方形成第二多晶硅层。可以将第二掺杂剂选择性地引入第一有源区上方的第二多晶硅层的一部分。在第一有源区上方的第二多晶硅层的部分和第一有源区上方的第一多晶硅层的部分可以被图案化以在第一有源区内形成第一栅极结构。在第二有源区上方的第二多晶硅层的部分和第二有源区上方的第一多晶硅层的部分可以被图案化以在第二有源区内形成第二栅极结构。

3. 发明授权

US6137145A Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon 有权
标题翻译：半导体形貌包括集成了多层多晶硅层的集成电路栅极导体
公开(公告)号：US6137145A
公开(公告)日：2000-10-24
申请号：US237773
申请日：1999-01-26
申请人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
发明人： Jon D. Cheek , Daniel Kadosh , Mark W. Michael
IPC分类号： H01L21/8234 , H01K29/76
CPC分类号： H01L21/82345
摘要： A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal. The first gate conductor may be doped with a first dopant that has a lower diffusion rate through polysilicon than a second dopant with which the second gate conductor is doped. The second polysilicon layer portion of the second gate conductor is substantially free of implanted dopants.
摘要翻译：提供包括并入双多晶硅层的集成电路栅极导体的半导体形貌。半导体形貌包括半导体衬底。第一栅极导体布置在第一栅极电介质上并位于半导体衬底之上，并且第二栅极导体布置在第二栅极电介质上并位于半导体衬底之上。半导体衬底可以包含通过场区域与第二有源区域横向分离的第一有源区域。第一栅极导体可以布置在第一有源区内，并且第二栅极导体可以布置在第二有源区内。每个栅极导体优选地包括布置在第一多晶硅层部分上的第二多晶硅层部分。第一栅极导体和第二栅极导体的厚度优选相等。第一栅极导体可以掺杂有第一掺杂剂，其通过多晶硅具有比掺杂第二栅极导体的第二掺杂物更低的扩散速率。第二栅极导体的第二多晶硅层部分基本上没有注入的掺杂剂。

4. 发明授权

US06399493B1 Method of silicide formation by silicon pretreatment 有权
标题翻译：硅预处理硅化物形成方法
公开(公告)号：US06399493B1
公开(公告)日：2002-06-04
申请号：US09860141
申请日：2001-05-17
申请人： Robert Dawson , Jon D. Cheek , John G. Pellerin
发明人： Robert Dawson , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L29/665
摘要： Various methods of fabricating a silicide film and structures incorporating the same are provided. In one aspect, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide. The roughing of the silicon surface facilitates metal-silicide reactions.
摘要翻译：提供了制造硅化物膜的各种方法和结合其的结构。一方面，提供一种制造硅化物膜的方法，其包括在各向同性和各向异性蚀刻条件之间提供硅表面和蚀刻硅表面以在其上限定多个倾斜表面，从而增加硅表面的表面积。在多个倾斜表面上沉积硅化物形成材料，并加热硅表面以使硅化物形成材料与其反应并形成硅化物。硅表面的粗加工有助于金属硅化物反应。

5. 发明授权

US6104064A Asymmetrical transistor structure 有权
标题翻译：不对称晶体管结构
公开(公告)号：US6104064A
公开(公告)日：2000-08-15
申请号：US306508
申请日：1999-05-06
申请人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
发明人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28211 , H01L21/28176 , H01L29/66659 , H01L29/7835
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

6. 发明授权

US07179745B1 Method for offsetting a silicide process from a gate electrode of a semiconductor device 失效
标题翻译：将硅化物工艺与半导体器件的栅电极相抵消的方法
公开(公告)号：US07179745B1
公开(公告)日：2007-02-20
申请号：US10860100
申请日：2004-06-04
申请人： Andrew M. Waite , Jon D. Cheek , David Brown
发明人： Andrew M. Waite , Jon D. Cheek , David Brown
IPC分类号： H01L21/311
CPC分类号： H01L29/7843 , H01L29/665 , H01L29/6653 , H01L29/66772
摘要： A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.
摘要翻译：一种用于在具有多晶硅栅电极，衬底中的源极和漏极区域以及衬底中的源极和漏极延伸部分的半导体器件上偏移硅化物的方法，在多晶硅栅电极的侧壁上采用氮化钛侧壁间隔物。氮化钛侧壁间隔物防止了在氧化过程中在源极和漏极延伸部分顶部的硅化物生长。然后通过蚀刻工艺去除氮化钛侧壁间隔物，该蚀刻工艺不蚀刻在源极和漏极区域以及多晶硅栅极电极中形成的硅化物区域。在移除氮化钛侧壁间隔物之后，可以将低k层间介电层或应力衬垫沉积在器件的顶部以增强器件性能。

7. 发明授权

US06720227B1 Method of forming source/drain regions in a semiconductor device 失效
标题翻译：在半导体器件中形成源/漏区的方法
公开(公告)号：US06720227B1
公开(公告)日：2004-04-13
申请号：US10059615
申请日：2002-01-29
申请人： Daniel Kadosh , Jon D. Cheek , James F. Buller , Basab Bandyopadhyay
发明人： Daniel Kadosh , Jon D. Cheek , James F. Buller , Basab Bandyopadhyay
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/7833
摘要： A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.
摘要翻译：提供了一种在半导体器件中形成源极/漏极区域的方法。在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，通过至少执行以下步骤在衬底中邻近栅电极形成源极/漏极区：执行两个离子注入工艺以形成用于并且执行第三离子注入工艺以进一步形成用于该器件的源极/漏极区域。本发明可以使用各种N型和P型掺杂剂原子，例如砷，磷，硼和二氟化硼。

8. 发明授权

US06426262B1 Method of analyzing the effects of shadowing of angled halo implants 失效
标题翻译：分析角度晕轮植入物阴影效应的方法
公开(公告)号：US06426262B1
公开(公告)日：2002-07-30
申请号：US09644735
申请日：2000-08-23
申请人： Mark Brandon Fuselier , Jon D. Cheek , Frederick N. Hause , Marilyn I. Wright
发明人： Mark Brandon Fuselier , Jon D. Cheek , Frederick N. Hause , Marilyn I. Wright
IPC分类号： H01L218236
CPC分类号： H01L29/66492 , H01L21/26586
摘要： The present invention is directed to a method that comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.
摘要翻译：本发明涉及一种包括形成多个晶体管的方法，每个晶体管具有至少一个栅电极，并且在晶体管中形成晕圈注入区，同时改变光晕注入角，掩模层高度和屏蔽层与晶体管的栅电极的横向偏移。该方法还包括确定晶体管中的至少一些晶体管的电性能特征，其中，所述卤素注入角，掩模层高度和掩模层的横向偏移中的至少一个不同，以及将所确定的电性能特性晶体管。

9. 发明授权

US06406964B1 Method of controlling junction recesses in a semiconductor device 有权
标题翻译：控制半导体器件中的接合凹部的方法
公开(公告)号：US06406964B1
公开(公告)日：2002-06-18
申请号：US09704008
申请日：2000-11-01
申请人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
发明人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/665 , H01L29/7833
摘要： The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implant process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.
摘要翻译：本发明涉及一种形成晶体管的方法。在一个实施例中，所述方法包括提供衬底，所述衬底被掺杂有第一类型的掺杂剂材料，在由所述隔离结构限定的所述衬底的有源区域中的所述衬底上形成晶体管，以及执行至少一个离子注入在与晶体管的栅电极相邻的衬底中注入掺杂剂原子的工艺。该方法还包括在晶体管上执行与第一类掺杂剂材料相反类型的掺杂剂材料的至少两个成角度的离子注入工艺，并执行至少一个退火工艺。

10. 发明授权

US06316302B1 Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant 有权
标题翻译：各向同性蚀刻要用于NMOS源极/漏极注入和PMOS LDD植入物的侧壁间隔物
公开(公告)号：US06316302B1
公开(公告)日：2001-11-13
申请号：US09604051
申请日：2000-06-26
申请人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
发明人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/823864 , H01L29/6656
摘要： A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
摘要翻译：提供了一种用于各向同性蚀刻侧壁间隔物对以减少每个侧壁间隔物的横向厚度的方法。在一个实施例中，第一和第二对侧壁间隔件同时形成在相应的第一和第二栅极导体的相对的侧壁表面上。第一和第二栅极导体分别在半导体衬底的隔离的第一和第二有源区域上横向间隔开。有利地，在形成PMOS晶体管的NMOS晶体管和LDD区域的源极和漏极区域期间，单个侧壁间隔物对被用作掩模结构。也就是说，在减少侧壁间隔物的横向厚度之前，n +源极/漏极（“S / D”）植入物在第一对侧壁间隔物的外侧边缘上自对准。然而，在间隔物厚度减小之后，p-LDD植入物自对准到第二对侧壁间隔物的外侧边缘。因此，不需要在栅极导体的侧壁表面附近形成多对侧壁间隔件，以改变注入区域和后续集成电路的栅极导体之间的间隔。

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