专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6104064A Asymmetrical transistor structure 有权
标题翻译：不对称晶体管结构
公开(公告)号：US6104064A
公开(公告)日：2000-08-15
申请号：US306508
申请日：1999-05-06
申请人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
发明人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28211 , H01L21/28176 , H01L29/66659 , H01L29/7835
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

2. 发明授权

US5981357A Semiconductor trench isolation with improved planarization methodology 失效
标题翻译：具有改进的平面化方法的半导体沟槽隔离
公开(公告)号：US5981357A
公开(公告)日：1999-11-09
申请号：US877000
申请日：1997-06-16
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

3. 发明授权

US5904539A Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties 失效
标题翻译：半导体沟槽隔离工艺导致硅台面具有增强的机械和电学性能
公开(公告)号：US5904539A
公开(公告)日：1999-05-18
申请号：US619004
申请日：1996-03-21
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

4. 发明授权

US6137182A Method of reducing via and contact dimensions beyond photolithography equipment limits 有权
标题翻译：降低光刻设备限制以外的通孔和接触尺寸的方法
公开(公告)号：US6137182A
公开(公告)日：2000-10-24
申请号：US137471
申请日：1998-08-20
申请人： Fred N. Hause , Mark I. Gardner , Robert Dawson
发明人： Fred N. Hause , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76816
摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprised of polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall, preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covering peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.
摘要翻译：一种用于形成层间接触的半导体工艺。半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。在电介质层上形成优选由多晶硅或氮化硅构成的边界层。然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁。然后在环形侧壁上形成间隔结构，优选地，间隔物结构通过化学气相沉积间隔物材料形成，并且各向异性地蚀刻间隔物材料，以便在具有最小过氧化物的平面区域中刚好清除。间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

5. 发明授权

US5843625A Method of reducing via and contact dimensions beyond photolithography equipment limits 失效
标题翻译：降低光刻设备限制以外的通孔和接触尺寸的方法
公开(公告)号：US5843625A
公开(公告)日：1998-12-01
申请号：US685144
申请日：1996-07-23
申请人： Fred N. Hause , Mark I. Gardner , Robert Dawson
发明人： Fred N. Hause , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/768 , G03F7/00
CPC分类号： H01L21/76816
摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprising polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall. Preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covers peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.
摘要翻译：一种用于形成层间接触的半导体工艺。半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。优选地包括多晶硅或氮化硅的边界层形成在电介质层上。然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁。然后在环形侧壁上形成间隔结构。优选地，通过化学气相沉积间隔物材料并且各向异性地蚀刻间隔物材料来形成间隔结构，以便在具有最小过蚀刻的平面区域中刚好清除。间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

6. 发明授权

US5783458A Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer 失效
标题翻译：具有氮化氧化物的非对称p沟道晶体管被图案化以允许选择形成生长侧壁间隔物
公开(公告)号：US5783458A
公开(公告)日：1998-07-21
申请号：US720731
申请日：1996-10-01
申请人： Daniel Kadosh , Robert Dawson , Fred N. Hause
发明人： Daniel Kadosh , Robert Dawson , Fred N. Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/265 , H01L21/44
CPC分类号： H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/66659 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current-a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

7. 发明授权

US5885877A Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效
标题翻译：复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质
公开(公告)号：US5885877A
公开(公告)日：1999-03-23
申请号：US837581
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.
摘要翻译：复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层，并通过原位沉积氮掺杂的第一多晶硅层。完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。

8. 发明授权

US5759897A Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region 失效
标题翻译：制造具有轻掺杂和重掺杂漏极区域和超重掺杂源极区域的不对称晶体管的方法
公开(公告)号：US5759897A
公开(公告)日：1998-06-02
申请号：US711382
申请日：1996-09-03
申请人： Daniel Kadosh , Mark I. Gardner , Robert Dawson
发明人： Daniel Kadosh , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/7835 , H01L29/665
摘要： An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming a drain-side spacer adjacent to the second sidewall, and applying a third ion implantation to convert the heavily doped source region into an ultra-heavily doped source region and to convert a portion of the lightly doped drain region outside the drain-side spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.
摘要翻译：公开了一种包括轻掺杂和重掺杂漏极区域和超重掺杂源极区域的非对称IGFET。优选地，轻掺杂漏极区域和超重掺杂源极区域提供通道结。制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以基本上转换将所有轻掺杂源区域全部掺入重掺杂源区，而不掺杂轻掺杂漏极区，形成与第二侧壁相邻的漏极侧隔离层，以及施加第三离子注入以将重掺杂源区转换成超掺杂源区，并且将漏极侧间隔物外部的轻掺杂漏极区域的一部分转换为重掺杂漏极区域，而不将漏极侧间隔物下方的轻掺杂漏极区域的一部分掺杂。有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

9. 发明授权

US5654215A Method for fabrication of a non-symmetrical transistor 失效
标题翻译：制造非对称晶体管的方法
公开(公告)号：US5654215A
公开(公告)日：1997-08-05
申请号：US713388
申请日：1996-09-13
申请人： Mark I. Gardner , Daniel Kadosh , Robert Dawson
发明人： Mark I. Gardner , Daniel Kadosh , Robert Dawson
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823468 , H01L29/7835 , Y10S438/911
摘要： In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, a gate insulator and a gate electrode, such as a polysilicon, are formed over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls. A first dopant is implanted into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall. First and second symmetrical spacers are then formed adjacent the first and second sidewalls, respectively. A second dopant is implanted into the semiconductor substrate after forming the symmetrical spacers to provide a moderately-lightly doped drain region substantially aligned with the outer region of the second symmetrical spacer. After implanting the second dopant, first and second non-symmetrical spacers are formed adjacent the first and second sidewalls, respectively. A heavy dose of a third dopant is then implanted into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region. In another embodiment, a fourth dopant is implanted into the semiconductor substrate before forming the first and second symmetrical spacers further doping the lightly doped drain region.
摘要翻译：在本发明中，描述了用于制造非对称LDD-IGFET的方法。在一个实施例中，栅极绝缘体和诸如多晶硅的栅电极形成在半导体衬底之上，栅电极具有顶表面和相对的第一和第二侧壁。将第一掺杂剂注入到半导体衬底中以提供基本上与第二侧壁对齐的轻掺杂漏极区。然后分别在第一和第二侧壁附近形成第一和第二对称间隔物。在形成对称间隔物之后，将第二掺杂剂注入到半导体衬底中，以提供基本上与第二对称间隔物的外部区域对准的适度轻掺杂的漏区。在注入第二掺杂剂之后，分别在第一和第二侧壁附近形成第一和第二非对称间隔物。然后将大量的第三掺杂剂注入到半导体衬底中以提供重掺杂的源极区域和重掺杂的漏极区域。在另一个实施例中，在形成第一和第二对称间隔物之前将第四掺杂剂注入到半导体衬底中，进一步掺杂轻掺杂漏极区。

10. 发明授权

US06225151B1 Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion 失效
标题翻译：晶体管源极/漏极区域之下的氮衬垫以延迟掺杂剂扩散
公开(公告)号：US06225151B1
公开(公告)日：2001-05-01
申请号：US08871469
申请日：1997-06-09
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2122
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28176 , H01L21/28202 , H01L21/823814 , H01L29/1033 , H01L29/518 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7833
摘要： A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source. Such a liner is particularly advantageous for boron-doped source/drain regions, and may be combined with N-channel IGFETs formed without such liners.
摘要翻译：基本上在IGFET的源极/漏极区域下方大致相邻地形成的氮注入区域形成衬垫，以在随后的热处理操作（例如退火步骤）期间阻止源极/漏极掺杂剂原子的扩散。可以在将源极/漏极掺杂剂注入较低深度之前通过将氮注入给定深度来形成氮衬垫。也可以将氮气引入到栅电极下面的IGFET沟道区域的区域中，以阻止源极/漏极掺杂剂的随后的横向扩散。可以使用一个或多个成角度的注入步骤来实现这种氮引入，或者可以通过使用与栅电极对准的垂直注入形成的注入氮层退火来实现。衬垫可以形成在IGFET的漏极侧或源极和漏极两侧，并且可以形成在漏极和/或源极的重掺杂区域的轻掺杂区域下方。这种衬垫对于硼掺杂的源极/漏极区域是特别有利的，并且可以与没有这样的衬垫形成的N沟道IGFET组合。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式