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1. 发明授权

US06399493B1 Method of silicide formation by silicon pretreatment 有权
标题翻译：硅预处理硅化物形成方法
公开(公告)号：US06399493B1
公开(公告)日：2002-06-04
申请号：US09860141
申请日：2001-05-17
申请人： Robert Dawson , Jon D. Cheek , John G. Pellerin
发明人： Robert Dawson , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L29/665
摘要： Various methods of fabricating a silicide film and structures incorporating the same are provided. In one aspect, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide. The roughing of the silicon surface facilitates metal-silicide reactions.
摘要翻译：提供了制造硅化物膜的各种方法和结合其的结构。一方面，提供一种制造硅化物膜的方法，其包括在各向同性和各向异性蚀刻条件之间提供硅表面和蚀刻硅表面以在其上限定多个倾斜表面，从而增加硅表面的表面积。在多个倾斜表面上沉积硅化物形成材料，并加热硅表面以使硅化物形成材料与其反应并形成硅化物。硅表面的粗加工有助于金属硅化物反应。

2. 发明授权

US06406964B1 Method of controlling junction recesses in a semiconductor device 有权
标题翻译：控制半导体器件中的接合凹部的方法
公开(公告)号：US06406964B1
公开(公告)日：2002-06-18
申请号：US09704008
申请日：2000-11-01
申请人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
发明人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/665 , H01L29/7833
摘要： The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implant process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.
摘要翻译：本发明涉及一种形成晶体管的方法。在一个实施例中，所述方法包括提供衬底，所述衬底被掺杂有第一类型的掺杂剂材料，在由所述隔离结构限定的所述衬底的有源区域中的所述衬底上形成晶体管，以及执行至少一个离子注入在与晶体管的栅电极相邻的衬底中注入掺杂剂原子的工艺。该方法还包括在晶体管上执行与第一类掺杂剂材料相反类型的掺杂剂材料的至少两个成角度的离子注入工艺，并执行至少一个退火工艺。

3. 发明授权

US07091106B2 Method of reducing STI divot formation during semiconductor device fabrication 有权
标题翻译：在半导体器件制造期间减少STI纹路形成的方法
公开(公告)号：US07091106B2
公开(公告)日：2006-08-15
申请号：US10791759
申请日：2004-03-04
申请人： Douglas J. Bonser , Johannes F. Groschopf , Srikanteswara Dakshina-Murthy , John G. Pellerin , Jon D. Cheek
发明人： Douglas J. Bonser , Johannes F. Groschopf , Srikanteswara Dakshina-Murthy , John G. Pellerin , Jon D. Cheek
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.
摘要翻译：通过使用非常薄的氮化物抛光停止层（例如不厚于400）来消除或显着降低STI形成。非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。

4. 发明授权

US06580122B1 Transistor device having an enhanced width dimension and a method of making same 有权
标题翻译：具有增强的宽度尺寸的晶体管器件及其制造方法
公开(公告)号：US06580122B1
公开(公告)日：2003-06-17
申请号：US09812521
申请日：2001-03-20
申请人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
发明人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L2976
CPC分类号： G01N27/414
摘要： The present invention is directed to a transistor having an enhanced width dimension and a method of making same. In one illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure formed in the substrate, the isolation structure defining a recess thereabove, a gate electrode and a gate insulation layer positioned above the substrate, a portion of the gate electrode and the gate insulation layer extending into the recess above the recessed isolation structure, and a source region and a drain region formed in the substrate. In another illustrative embodiment, the transistor comprises a semiconducting substrate, a recessed isolation structure that defines an active area having an upper surface and an exposed sidewall surface, a gate insulation layer and a gate electrode positioned above a portion of the upper surface and a portion of the exposed sidewall surface of the active area, and a source region and a drain region formed in the active area.
摘要翻译：本发明涉及一种具有增强的宽度尺寸的晶体管及其制造方法。在一个说明性实施例中，晶体管包括半导体衬底，形成在衬底中的凹陷隔离结构，隔离结构在其上限定凹陷，栅电极和位于衬底上方的栅极绝缘层，栅电极的一部分和栅极绝缘层延伸到凹陷隔离结构上方的凹部中，以及形成在衬底中的源极区域和漏极区域。在另一示例性实施例中，晶体管包括半导体衬底，限定具有上表面和暴露侧壁表面的有源区的凹陷隔离结构，位于上表面的一部分上方的栅绝缘层和栅电极，的有源区域的暴露的侧壁表面，以及形成在有源区域中的源极区域和漏极区域。

5. 发明授权

US07253484B2 Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
标题翻译：低功耗多通道全耗尽量子阱CMOSFET
公开(公告)号：US07253484B2
公开(公告)日：2007-08-07
申请号：US11445345
申请日：2006-06-02
申请人： James N. Pan , John G. Pellerin , Jon Cheek
发明人： James N. Pan , John G. Pellerin , Jon Cheek
IPC分类号： H01L27/088 , H01L29/78 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
摘要翻译：多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

6. 发明授权

US06780776B1 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer 有权
标题翻译：氮化物偏移间隔物，通过使用多重再氧化层作为蚀刻停止层来最小化硅凹槽
公开(公告)号：US06780776B1
公开(公告)日：2004-08-24
申请号：US10023328
申请日：2001-12-20
申请人： Wen-Jie Qi , John G. Pellerin , William G. En , Mark W. Michael , Darin A. Chan
发明人： Wen-Jie Qi , John G. Pellerin , William G. En , Mark W. Michael , Darin A. Chan
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/31116 , H01L21/3185 , H01L29/6656
摘要： A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.
摘要翻译：形成半导体器件的方法在衬底上提供栅电极，并在衬底和栅电极上形成多晶硅再氧化层。氮化物层沉积在多晶硅再氧化层上并各向异性蚀刻。多晶硅再氧化层上的蚀刻停止，在栅电极上形成氮化物偏移间隔物。使用多晶硅再氧化层作为蚀刻停止层防止在氮化物层下方的硅衬底的气蚀，同时允许形成偏移间隔物。

7. 发明授权

US5986344A Anti-reflective coating layer for semiconductor device 失效
标题翻译：半导体器件抗反射涂层
公开(公告)号：US5986344A
公开(公告)日：1999-11-16
申请号：US59420
申请日：1998-04-14
申请人： Ramkumar Subramanion , Suzette K. Pangrle , John G. Pellerin , Ernesto A. Gallardo
发明人： Ramkumar Subramanion , Suzette K. Pangrle , John G. Pellerin , Ernesto A. Gallardo
IPC分类号： H01L21/027 , H01L23/58
CPC分类号： H01L21/0276 , Y10S438/952
摘要： In a photo-lithographic step for providing contact points to lower layers of a semiconductor device, an anti-reflective coating (ARC) layer, such as FLARE 2.0.TM., is used to provide a good contact points to an underlayer. After the contact points are made, the anti-reflective coating layer is removed, with the removal being performed in a same step in which a photo-resist is removed from the semiconductor device. In an alternative configuration, the ARC layer remains in the semiconductor device after the fabrication process is competed, thereby acting as an interlayer dielectric during operation of the semiconductor device.
摘要翻译：在用于向半导体器件的较低层提供接触点的光刻步骤中，使用诸如FLARE 2.0 TM的抗反射涂层（ARC）层来提供与底层的良好接触点。在制成接触点之后，去除抗反射涂层，在与半导体器件中去除光致抗蚀剂的相同步骤中进行去除。在替代配置中，在制造工艺竞争之后ARC层保留在半导体器件中，从而在半导体器件的操作期间用作层间电介质。

8. 发明授权

US07723192B2 Integrated circuit long and short channel metal gate devices and method of manufacture 有权
标题翻译：集成电路长短通道金属栅极器件及其制造方法
公开(公告)号：US07723192B2
公开(公告)日：2010-05-25
申请号：US12048414
申请日：2008-03-14
申请人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
发明人： Richard J. Carter , Michael J. Hargrove , George J. Kluth , John G. Pellerin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823456 , H01L21/28114 , H01L21/823468 , H01L29/4933 , H01L29/66545
摘要： A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench.
摘要翻译：提供了一种用于制造集成电路的方法，该集成电路包括短沟道（SC）器件和每个由层间电介质覆盖的长沟道（LC）器件。 SC器件具有SC栅极堆叠，LC器件最初具有虚拟栅极。在一个实施例中，该方法包括以下步骤：去除伪栅极以形成LC器件沟槽，以及在SC器件和LC器件上沉积金属栅极材料。金属栅极材料接触SC栅极堆叠并且基本上填充LC器件沟槽。

9. 发明授权

US07223698B1 Method of forming a semiconductor arrangement with reduced field-to active step height 失效
标题翻译：形成具有减小的场到活动台阶高度的半导体装置的方法
公开(公告)号：US07223698B1
公开(公告)日：2007-05-29
申请号：US11053910
申请日：2005-02-10
申请人： Douglas J. Bonser , Srikanteswara Dakshina-Murthy , Mark C. Kelling , John G. Pellerin , Johannes F. Groschopf , Edward Asuka Nomura
发明人： Douglas J. Bonser , Srikanteswara Dakshina-Murthy , Mark C. Kelling , John G. Pellerin , Johannes F. Groschopf , Edward Asuka Nomura
IPC分类号： H01L21/311
CPC分类号： H01L21/76232
摘要： A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.
摘要翻译：在硅衬底中形成浅沟槽隔离（STI）区域的方法产生在硅衬底的顶表面上方延伸的STI区域。在基板上形成平坦化介质层，并在场氧化物区域上方延伸。平面化电介质层通过化学机械抛光或覆盖层回蚀除去，例如，以及在衬底的顶表面和活性区上延伸的场氧化物区域的那些部分。从而消除或显着降低台阶高度。

10. 发明授权

US07074657B2 Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
标题翻译：低功耗多通道全耗尽量子阱CMOSFET
公开(公告)号：US07074657B2
公开(公告)日：2006-07-11
申请号：US10706948
申请日：2003-11-14
申请人： James N. Pan , John G. Pellerin , Jon Cheek
发明人： James N. Pan , John G. Pellerin , Jon Cheek
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
摘要翻译：多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

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