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    • 1. 发明授权
    • Method for offsetting a silicide process from a gate electrode of a semiconductor device
    • 将硅化物工艺与半导体器件的栅电极相抵消的方法
    • US07179745B1
    • 2007-02-20
    • US10860100
    • 2004-06-04
    • Andrew M. WaiteJon D. CheekDavid Brown
    • Andrew M. WaiteJon D. CheekDavid Brown
    • H01L21/311
    • H01L29/7843H01L29/665H01L29/6653H01L29/66772
    • A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.
    • 一种用于在具有多晶硅栅电极,衬底中的源极和漏极区域以及衬底中的源极和漏极延伸部分的半导体器件上偏移硅化物的方法,在多晶硅栅电极的侧壁上采用氮化钛侧壁间隔物。 氮化钛侧壁间隔物防止了在氧化过程中在源极和漏极延伸部分顶部的硅化物生长。 然后通过蚀刻工艺去除氮化钛侧壁间隔物,该蚀刻工艺不蚀刻在源极和漏极区域以及多晶硅栅极电极中形成的硅化物区域。 在移除氮化钛侧壁间隔物之后,可以将低k层间介电层或应力衬垫沉积在器件的顶部以增强器件性能。