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1. 发明授权

US06463570B1 Apparatus and method for verifying process integrity 有权
标题翻译：验证过程完整性的装置和方法
公开(公告)号：US06463570B1
公开(公告)日：2002-10-08
申请号：US09625620
申请日：2000-07-26
申请人： Michael J. Dunn , Mark Brandon Fuselier
发明人： Michael J. Dunn , Mark Brandon Fuselier
IPC分类号： G06F1750
CPC分类号： H01L22/14 , H01L22/34
摘要： An apparatus and method for verifying a process step in the fabrication of an integrated circuit device is implemented. A ring oscillator is fabricated on the dice constituting the integrated circuit device being manufactured. The ring oscillator structure is adapted for sensitizing the ring oscillator to variations in the process step being verified. During test of the wafer containing the dice, a scan of the frequency of the ring oscillator across the wafer for each die under test is made. Deviations in the ring oscillator frequency from a preselected nominal value delimit regions of the wafer for which the process step is marginal.
摘要翻译：实现了用于验证集成电路器件的制造中的工艺步骤的装置和方法。在构成正在制造的集成电路器件的骰子上制造环形振荡器。环形振荡器结构适于使环形振荡器对正在验证的工艺步骤中的变化进行敏感。在包含骰子的晶片的测试期间，对每个待测试晶片的晶片周期进行环形振荡器的频率的扫描。来自预选的标称值的环形振荡器频率的偏差限制了晶片的过程步骤边缘的区域。

2. 发明授权

US06410350B1 Detecting die speed variations 有权
标题翻译：检测模具速度变化
公开(公告)号：US06410350B1
公开(公告)日：2002-06-25
申请号：US09607150
申请日：2000-06-29
申请人： Mark Brandon Fuselier , Stephen Doug Ray , Michael James Dunn , Roger T. Williams , Michael V. Fenske
发明人： Mark Brandon Fuselier , Stephen Doug Ray , Michael James Dunn , Roger T. Williams , Michael V. Fenske
IPC分类号： H01L2166
CPC分类号： G11C29/025 , G01R31/3016 , G01R31/31707 , G01R31/31725 , G11C29/006 , G11C29/50012
摘要： An apparatus and method for detecting speed variations across a die, a flash field, i.e., multiple dies, and multiple flash fields. In one embodiment, a method comprises the step of inserting a plurality of functional circuits at strategic locations across a die or flash field or multiple flash fields where each of the plurality of functional circuits generates data, e.g., values, frequency, etc., correlated to the die speeds at the strategic locations. The method further comprises reading the data generated by the plurality of functional circuits that may be correlated to the die speeds at the strategic locations. Speed variations across the die or flash field or multiple flash fields may then be subsequently detected based on the data generated by the plurality of functional circuits. Upon analyzing the data generated by the plurality of functional circuits, adjustments may be made to the manufacturing process to improve the number of acceptable integrated circuits or chips disposed in the dies.
摘要翻译：一种用于检测管芯上的速度变化，闪光场，即多个管芯和多个闪光场的装置和方法。在一个实施例中，一种方法包括以下步骤：跨越管芯或闪存场或多个闪存场的战略位置插入多个功能电路，其中多个功能电路中的每一个产生数据，例如值，频率等相关在战略地点的死亡速度。该方法还包括读取由多个功能电路产生的数据，这些数据可能与战略位置处的模具速度相关。然后可以基于由多个功能电路产生的数据随后检测管芯或闪光场或多个闪光场的速度变化。在分析由多个功能电路产生的数据时，可以对制造过程进行调整，以改善设置在管芯中的可接受集成电路或芯片的数量。

3. 发明授权

US06287877B1 Electrically quantifying transistor spacer width 失效
标题翻译：电子量子化晶体管间隔物宽度
公开(公告)号：US06287877B1
公开(公告)日：2001-09-11
申请号：US09668524
申请日：2000-09-22
申请人： Roger Williams , Mark Brandon Fuselier , Michael Verne Fenske
发明人： Roger Williams , Mark Brandon Fuselier , Michael Verne Fenske
IPC分类号： G01R3126
CPC分类号： G01R31/275 , G01R31/2621
摘要： A method for electrically quantifying a semiconductor device's spacers' width. In one embodiment, a method comprises the step of measuring a resistance across a region of interest of each of a plurality of semiconductor structures including the semiconductor device in question, where the region of interest may be a source or drain region of the semiconductor structure or may be one of a plurality of lightly doped drain regions of the semiconductor structure. The method further comprises determining a width of one of a plurality of lightly doped drain regions of the semiconductor device from the resistance across the region of interest of each of the plurality of semiconductor structures. The method further comprises determining the semiconductor device's spacers' width from the width of one of the plurality of lightly doped drain regions of the semiconductor device.
摘要翻译：一种用于电化学半导体器件间隔物宽度的方法。在一个实施例中，一种方法包括测量包括所讨论的半导体器件的多个半导体结构中的每一个的感兴趣区域的电阻的步骤，其中感兴趣区域可以是半导体结构的源极或漏极区域，或可以是半导体结构的多个轻掺杂漏区中的一个。该方法还包括从跨越多个半导体结构中的每一个的感兴趣区域的电阻确定半导体器件的多个轻掺杂漏极区域中的一个的宽度。该方法还包括从半导体器件的多个轻掺杂漏区之一的宽度确定半导体器件的间隔物的宽度。

4. 发明授权

US06570228B1 Method and apparatus for electrically measuring insulating film thickness 失效
标题翻译：绝缘膜厚度的电气测量方法和装置
公开(公告)号：US06570228B1
公开(公告)日：2003-05-27
申请号：US10052060
申请日：2002-01-17
申请人： Mark Brandon Fuselier , Roger Thomas Williams , Michael Verne Fenske
发明人： Mark Brandon Fuselier , Roger Thomas Williams , Michael Verne Fenske
IPC分类号： H01L218238
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method and an apparatus for measuring insulating film thickness, such as the width of sidewall spacers. The method includes positioning a first test structure having a first resistance at a first location on a semiconductor wafer and positioning a second test structure having a second resistance different from the first resistance at a second location on the semiconductor wafer. The method also includes measuring the first resistance of the first test structure and measuring the second resistance of the second test structure. The method also includes determining an average characteristic of the first test structure and the second test structure, other than resistance, based on the first resistance of the first test structure and the second resistance of the second test structure.
摘要翻译：用于测量绝缘膜厚度的方法和装置，例如侧壁间隔件的宽度。该方法包括在半导体晶片上的第一位置处定位具有第一电阻的第一测试结构，并且在半导体晶片上的第二位置处定位具有不同于第一电阻的第二电阻的第二测试结构。该方法还包括测量第一测试结构的第一电阻并测量第二测试结构的第二电阻。该方法还包括基于第一测试结构的第一电阻和第二测试结构的第二电阻来确定除电阻之外的第一测试结构和第二测试结构的平均特性。

5. 发明授权

US06426262B1 Method of analyzing the effects of shadowing of angled halo implants 失效
标题翻译：分析角度晕轮植入物阴影效应的方法
公开(公告)号：US06426262B1
公开(公告)日：2002-07-30
申请号：US09644735
申请日：2000-08-23
申请人： Mark Brandon Fuselier , Jon D. Cheek , Frederick N. Hause , Marilyn I. Wright
发明人： Mark Brandon Fuselier , Jon D. Cheek , Frederick N. Hause , Marilyn I. Wright
IPC分类号： H01L218236
CPC分类号： H01L29/66492 , H01L21/26586
摘要： The present invention is directed to a method that comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.
摘要翻译：本发明涉及一种包括形成多个晶体管的方法，每个晶体管具有至少一个栅电极，并且在晶体管中形成晕圈注入区，同时改变光晕注入角，掩模层高度和屏蔽层与晶体管的栅电极的横向偏移。该方法还包括确定晶体管中的至少一些晶体管的电性能特征，其中，所述卤素注入角，掩模层高度和掩模层的横向偏移中的至少一个不同，以及将所确定的电性能特性晶体管。

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