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1. 发明授权

US6104064A Asymmetrical transistor structure 有权
标题翻译：不对称晶体管结构
公开(公告)号：US6104064A
公开(公告)日：2000-08-15
申请号：US306508
申请日：1999-05-06
申请人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
发明人： Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28211 , H01L21/28176 , H01L29/66659 , H01L29/7835
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

2. 发明授权

US5926693A Two level transistor formation for optimum silicon utilization 失效
标题翻译：用于最佳硅利用的两级晶体管形成
公开(公告)号：US5926693A
公开(公告)日：1999-07-20
申请号：US788376
申请日：1997-01-27
申请人： Mark I. Gardner , Fred N. Hause , Jon D. Cheek
发明人： Mark I. Gardner , Fred N. Hause , Jon D. Cheek
IPC分类号： H01L27/07 , H01L27/088 , H01L21/00
CPC分类号： H01L27/0705 , H01L27/088
摘要： A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth. The trench depth is preferably greater than a junction depth of the source/drain structures. In one embodiment, the formation of the trench transistor further includes, prior to the thermal oxidation of the trench floor, forming first and second ldd structures within the first and second trench ldd regions of the substrate. The first and second trench ldd structures provide conductive paths that extend from a trench channel region located beneath the trench floor to the first and the second shared source/drain structures respectively.
摘要翻译：一种半导体工艺，其中沟槽晶体管形成在一对平面晶体管之间，使得沟槽晶体管的源极/漏极区域与平面晶体管的源极/漏极区域共享。提供衬底，并且在衬底的上表面上形成第一和第二平面晶体管。沟槽晶体管的栅极电介质在衬底的上表面下方垂直位移。沟槽晶体管与第一平面晶体管共享第一共享源极/漏极结构，并且与第二平面晶体管共享第二共享源极/漏极结构。沟槽晶体管的形成优选地包括以下步骤：将沟槽蚀刻到衬底中，热氧化沟槽的底部以形成沟槽栅极电介质，并用导电材料填充沟槽以形成沟槽栅极结构。沟槽底部通过沟槽深度在衬底的上表面下方垂直移位。沟槽深度优选地大于源极/漏极结构的结深度。在一个实施例中，沟槽晶体管的形成还包括在沟槽底板的热氧化之前，在衬底的第一和第二沟槽区域内形成第一和第二层结构。第一和第二沟槽层结构提供从位于沟槽底部下方的沟槽沟道区域分别延伸到第一和第二共享源极/漏极结构的导电路径。

3. 发明授权

US5893739A Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer 失效
标题翻译：具有硼迁移势垒的非对称P沟道晶体管和选择性地形成的侧壁间隔物
公开(公告)号：US5893739A
公开(公告)日：1999-04-13
申请号：US720728
申请日：1996-10-01
申请人： Daniel Kadosh , Fred N. Hause , Jon D. Cheek
发明人： Daniel Kadosh , Fred N. Hause , Jon D. Cheek
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/7835 , H01L29/7836
摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
摘要翻译：提供了用于产生p沟道和/或n沟道晶体管的各种工艺。因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。据此，本方法采用各种技术形成不对称晶体管。各种技术采用根据所需LDD结果而变化的处理步骤。首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。可以存在许多其它修改和替代的处理步骤，其全部在此描述。不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。

4. 发明授权

US06365943B1 High density integrated circuit 有权
公开(公告)号：US06365943B1
公开(公告)日：2002-04-02
申请号：US09157644
申请日：1998-09-21
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L2976
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

5. 发明授权

US5770483A Multi-level transistor fabrication method with high performance drain-to-gate connection 失效
标题翻译：具有高性能漏极 - 栅极连接的多电平晶体管制造方法
公开(公告)号：US5770483A
公开(公告)日：1998-06-23
申请号：US729795
申请日：1996-10-08
申请人： Daniel Kadosh , Mark I. Gardner , Fred N. Hause
发明人： Daniel Kadosh , Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/768 , H01L21/822 , H01L23/48 , H01L27/06 , H01L21/00 , H01L21/84
CPC分类号： H01L27/0688 , H01L21/8221 , H01L23/485 , H01L23/535 , H01L2924/0002
摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between the drain region of an upper level transistor to the gate of a lower level transistor so as to effect a direct coupling between the output of one transistor to the input of another. Direct coupling in this fashion affords a lower propagation delay and therefore achieves the benefit of a higher performance, faster switching circuit.
摘要翻译：提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同层次的器件之间的互连上。因此，引入了高性能互连，由此在一个晶体管级内的特征之间使互连尽可能短以达到另一晶体管级内的特征。互连采用直接在上级晶体管的漏极区域到低级晶体管的栅极之间的通孔，以便实现一个晶体管的输出与另一晶体管的输入之间的直接耦合。以这种方式的直接耦合提供较低的传播延迟，从而实现更高性能，更快速的开关电路的益处。

6. 发明授权

US6046471A Ultra shallow junction depth transistors 失效
标题翻译：超浅结深度晶体管
公开(公告)号：US6046471A
公开(公告)日：2000-04-04
申请号：US744405
申请日：1996-11-07
申请人： Mark I. Gardner , Fred N. Hause , Daniel Kadosh
发明人： Mark I. Gardner , Fred N. Hause , Daniel Kadosh
IPC分类号： H01L21/265 , H01L21/336 , H01L31/119
CPC分类号： H01L29/66575 , H01L21/2652
摘要： A shallow junction MOS transistor comprising a semiconductor substrate having an upper region that includes a first and a second lightly doped region laterally displaced on either side of the channel region. The first and second lightly doped regions extend to a junction depth below the upper surface of the semiconductor substrate. A first and a second lightly doped impurity distribution are located within the first and second source/drain regions of the semiconductor substrate. The shallow junction transistor further includes a gate dielectric formed on an upper surface of the channel region of the semiconductor substrate. A conductive gate that includes a first and a second sidewall is formed on the gate dielectric. A gate insulator is formed in contact with the first and second sidewalls of the conductive gate. First and second source/drain structures are formed above the upper surface of the semiconductor substrate. The first and second source/drain structures are laterally displaced over the first and second lightly doped regions of the semiconductor substrate.
摘要翻译：一种浅结MOS晶体管，包括具有上部区域的半导体衬底，所述上部区域包括在沟道区域的任一侧上横向移位的第一和第二轻掺杂区域。第一和第二轻掺杂区域延伸到半导体衬底的上表面下方的结深度。第一和第二轻掺杂杂质分布位于半导体衬底的第一和第二源极/漏极区域内。浅结晶体管还包括形成在半导体衬底的沟道区的上表面上的栅极电介质。包括第一和第二侧壁的导电栅极形成在栅极电介质上。栅极绝缘体形成为与导电栅极的第一和第二侧壁接触。第一和第二源极/漏极结构形成在半导体衬底的上表面之上。第一和第二源极/漏极结构在半导体衬底的第一和第二轻掺杂区域上横向移位。

7. 发明授权

US5994779A Semiconductor fabrication employing a spacer metallization technique 失效
标题翻译：采用间隔金属化技术的半导体制造
公开(公告)号：US5994779A
公开(公告)日：1999-11-30
申请号：US850253
申请日：1997-05-02
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/528
CPC分类号： H01L21/76885 , H01L21/76838 , H01L23/5283 , H01L2924/0002
摘要： An integrated circuit fabrication process is provided in which an interconnect having a least one vertical sidewall surface is formed. The interconnect thusly formed allows for higher packing density within the ensuring integrated circuit since the interconnect requires less space to accommodate the same current density as an interconnect having sloped (i.e., non-vertical) sidewall surfaces. A semiconductor topography is provided which includes transistors arranged upon and within a silicon-based substrate. A first interlevel dielectric is deposited across the semiconductor topography, and portions of the dielectric are removed to form vias to select portions of the transistors. Conductive plugs are formed exclusively within the vias. An insulating material patterned with vertical sidewall surfaces is then formed across the first interlevel dielectric and a portion of the plugs. The insulating material is then patterned. Conductive material is then deposited across the patterned insulating material, the plug upper surfaces, and the first interlevel dielectric. A portion of the conductive material is anisotropically removed to form interconnects which are laterally adjacent to the sidewall surfaces of the insulating material. Each interconnect includes two surfaces, one of which is vertical to the underlying topography and the other of which extends a distance from the fist surface and links with an upper region of the surface in an arcuate pattern. The first lateral surface of the interconnect is directly adjacent to a sidewall surface of the insulating material and is therefore intended to be vertical. The second lateral surface extends a distance from the first lateral surface, constrained the limitations of deposition and not lithography.
摘要翻译：提供一种集成电路制造工艺，其中形成具有至少一个垂直侧壁表面的互连。这样形成的互连允许在确保集成电路内的更高的封装密度，因为互连需要更少的空间以适应与具有倾斜（即，非垂直）侧壁表面的互连件相同的电流密度。提供半导体形貌，其包括布置在硅基衬底上和内部的晶体管。第一层间电介质淀积跨半导体形貌，去除电介质的部分以形成通孔以选择晶体管的部分。导电插头仅在通孔内形成。然后，跨越第一层间电介质和一部分插塞形成图案化有垂直侧壁表面的绝缘材料。然后将绝缘材料图案化。导电材料然后沉积在图案化的绝缘材料，插塞上表面和第一层间电介质上。导电材料的一部分被各向异性地去除以形成横向邻近绝缘材料的侧壁表面的互连。每个互连包括两个表面，其中一个垂直于下面的地形，另一个表面与第一表面延伸一段距离，并以弓形图案与表面的上部区域连接。互连的第一侧表面直接邻近绝缘材料的侧壁表面，因此意图是垂直的。第二侧表面从第一侧表面延伸一段距离，限制了沉积的限制，而不是光刻。

8. 发明授权

US5851883A High density integrated circuit process 失效
标题翻译：高密度集成电路工艺
公开(公告)号：US5851883A
公开(公告)日：1998-12-22
申请号：US844975
申请日：1997-04-23
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L21/8234
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.
摘要翻译：在包括硅基层的半导体衬底的上表面上形成介电层的半导体工艺。此后，在电介质层的上表面上形成上硅层。然后对电介质层和上硅层进行构图以在基底硅层的上表面上形成第一和第二硅 - 电介质叠层。第一和第二硅 - 电介质堆叠在硅衬底的沟道区域的任一侧上横向移位，并且每个包括近侧壁和远侧壁。近侧侧壁与通道区域的各个边界大致重合。此后，分别在第一和第二硅 - 电介质堆叠的近侧和远侧壁上形成近端和远端间隔结构。然后在硅基层的暴露部分上在基底硅层的沟道区上形成栅极电介质层。然后选择性地去除位于基底硅层的相应源极/漏极区域之上的第一和第二硅 - 电介质叠层的部分。然后沉积硅以填充由所选择的堆叠移除产生的第一和第二空隙。硅沉积还在沟道区域上填充栅极电介质上方的硅栅极区域。此后，将杂质分布引入沉积的硅中。沉积的硅然后被平坦化以物理地隔离第一和第二空隙内的栅极区域内的硅，从而形成包括硅栅极结构和第一和第二源极/漏极结构的晶体管。

9. 发明授权

US5904539A Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties 失效
标题翻译：半导体沟槽隔离工艺导致硅台面具有增强的机械和电学性能
公开(公告)号：US5904539A
公开(公告)日：1999-05-18
申请号：US619004
申请日：1996-03-21
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

10. 发明授权

US5981357A Semiconductor trench isolation with improved planarization methodology 失效
标题翻译：具有改进的平面化方法的半导体沟槽隔离
公开(公告)号：US5981357A
公开(公告)日：1999-11-09
申请号：US877000
申请日：1997-06-16
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

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