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1. 发明授权

US06350321B1 UHV horizontal hot wall cluster CVD/growth design 失效
标题翻译：特高压水平热壁簇CVD /生长设计
公开(公告)号：US06350321B1
公开(公告)日：2002-02-26
申请号：US09207353
申请日：1998-12-08
申请人： Kevin K. Chan , Christopher P. D'Emic , Raymond M. Sicina , Paul M. Kozlowski , Margaret Manny , Sandip Tiwari
发明人： Kevin K. Chan , Christopher P. D'Emic , Raymond M. Sicina , Paul M. Kozlowski , Margaret Manny , Sandip Tiwari
IPC分类号： C23C1600
CPC分类号： H01L21/67225 , C23C14/56
摘要： A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H2O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace. Furthermore, before any wafers are placed into the transfer chamber, they are loaded into a load/unload chamber, which is the sole connection to the ambient air, to be purged and pumped so as to minimize particles and contamination.
摘要翻译：簇系统控制在硅衬底上沉积或生长的膜的界面性质。该系统包括多个水平石英腔或管，每个水平的石英腔或管可以容纳大量的晶片，传送室和装载/卸载室。可以在不同环境空气的情况下，在不同的管中顺序执行若干工艺步骤。传输室连接它们，并允许晶片在绝对控制的特高压环境中从一个管到另一个管输送，将任何污染（例如H 2 O）限制到小于单层。此外，每个管可以泵送到特高压压力状态，以避免管之间的进一步交叉污染或产生颗粒。由于某些过程需要升高的温度，因此将所有晶片垂直放置在石英舟上，以防止垂直炉中出现任何晶片下垂。此外，在将任何晶片放入转移室之前，它们被装载到与环境空气的唯一连接的装载/卸载室中，以被清除和泵送，以使颗粒和污染物最小化。

2. 发明授权

US07816224B2 Method for fabricating an ultra thin silicon on insulator 有权
标题翻译：用于制造绝缘体上的超薄硅的方法
公开(公告)号：US07816224B2
公开(公告)日：2010-10-19
申请号：US12042936
申请日：2008-03-05
申请人： Kevin K. Chan , Jakub Kedzierski , Raymond M. Sicina
发明人： Kevin K. Chan , Jakub Kedzierski , Raymond M. Sicina
IPC分类号： H01L21/76
CPC分类号： H01L29/66628 , H01L21/7624 , H01L29/66772 , H01L29/78654
摘要： In one embodiment, the invention is a method for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
摘要翻译：在一个实施例中，本发明是用于制造绝缘体上的超薄硅的方法。用于制造绝缘体上的超薄硅的方法的一个实施例包括提供硅层，在第一温度下使硅层与至少一种反应气体饱和，第一温度足够低以基本上防止发生任何涉及反应气体，并将第一温度升至第二温度，第二温度大约为反应气体的解离温度。

3. 发明授权

US07859060B2 Ultra thin silicon on insulator 有权
标题翻译：超薄硅绝缘体
公开(公告)号：US07859060B2
公开(公告)日：2010-12-28
申请号：US12535398
申请日：2009-08-04
申请人： Kevin K. Chan , Jakub Kedzierski , Raymond M. Sicina
发明人： Kevin K. Chan , Jakub Kedzierski , Raymond M. Sicina
IPC分类号： H01L29/94
CPC分类号： H01L29/66628 , H01L21/7624 , H01L29/66772 , H01L29/78654
摘要： In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
摘要翻译：在一个实施例中，本发明是用于制造绝缘体上的超薄硅的方法和装置。用于制造绝缘体上的超薄硅的方法的一个实施例包括提供硅层，在第一温度下使硅层与至少一种反应气体饱和，第一温度足够低以基本上防止发生任何涉及反应气体，并将第一温度升至第二温度，第二温度大约为反应气体的解离温度。

4. 发明授权

US08557670B1 SOI lateral bipolar junction transistor having a wide band gap emitter contact 有权
标题翻译：具有宽带隙发射极接触的SOI横向双极结型晶体管
公开(公告)号：US08557670B1
公开(公告)日：2013-10-15
申请号：US13605253
申请日：2012-09-06
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/8222
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。在堆叠周围形成介电隔离件。执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

5. 发明申请

US20130256757A1 SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT 审中-公开
标题翻译：具有宽带带隙发射体接触的SOI侧向双极晶体管
公开(公告)号：US20130256757A1
公开(公告)日：2013-10-03
申请号：US13433537
申请日：2012-03-29
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。在堆叠周围形成介电隔离件。执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

6. 发明授权

US08586441B1 Germanium lateral bipolar junction transistor 有权
标题翻译：锗横向双极结晶体管
公开(公告)号：US08586441B1
公开(公告)日：2013-11-19
申请号：US13611606
申请日：2012-09-12
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/331
CPC分类号： H01L29/6625 , H01L29/161 , H01L29/735
摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.
摘要翻译：使用绝缘体上的锗（GOI）衬底形成锗横向双极结型晶体管（BJT）。在GOI衬底的锗层的顶表面上沉积硅钝化层。随后形成浅沟槽隔离结构，非本征基区结构和基底间隔物。通过离子注入在锗层内形成锗发射极区，锗基区和锗集电极区。在硅钝化层中形成硅发射极区域，硅基区域和硅集电极区域。在可选地形成发射极接触区域和集电极接触区域之后，可以形成金属半导体合金区域。在硅基区和锗基区之间以及硅发射极区和锗发射极区之间提供少量载流子的宽间隙接触。

7. 发明授权

US06444592B1 Interfacial oxidation process for high-k gate dielectric process integration 有权
标题翻译：用于高k栅介质工艺集成的界面氧化工艺
公开(公告)号：US06444592B1
公开(公告)日：2002-09-03
申请号：US09597765
申请日：2000-06-20
申请人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Matthew W. Copel , Christopher P. D'Emic , Evgeni P. Gousev , Fenton Read McFeely , Joseph S. Newbury , Harald F. Okorn-Schmidt , Patrick R. Varekamp , Theodore H. Zabel
发明人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Matthew W. Copel , Christopher P. D'Emic , Evgeni P. Gousev , Fenton Read McFeely , Joseph S. Newbury , Harald F. Okorn-Schmidt , Patrick R. Varekamp , Theodore H. Zabel
IPC分类号： H01L21469
CPC分类号： H01L21/31691 , H01L28/56
摘要： A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.
摘要翻译：提供了一种将高k材料集成到CMOS处理方案中的方法。该方法包括在半导体衬底的器件区域上形成界面氧化物，氧氮化物和/或氮化物层，所述界面层的厚度小于10埃; 和（b）在所述界面氧化物，氧氮化物和/或氮化物层上形成高k电介质材料，所述高k电介质的介电常数k大于8。

8. 发明授权

US08558282B1 Germanium lateral bipolar junction transistor 有权
公开(公告)号：US08558282B1
公开(公告)日：2013-10-15
申请号：US13607672
申请日：2012-09-08
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/331
CPC分类号： H01L29/6625 , H01L29/161 , H01L29/735
摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.

9. 发明申请

US20130260526A1 SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT 有权
公开(公告)号：US20130260526A1
公开(公告)日：2013-10-03
申请号：US13605253
申请日：2012-09-06
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/8222
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

10. 发明申请

US20080017936A1 Semiconductor device structures (gate stacks) with charge compositions 审中-公开
标题翻译：具有电荷组成的半导体器件结构（栅极堆叠）
公开(公告)号：US20080017936A1
公开(公告)日：2008-01-24
申请号：US11477707
申请日：2006-06-29
申请人： Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Leland Chang , Christopher P. D'Emic , Martin M. Frank , Evgeni Gusev , Jin-Ping Han , Rajarao Jammy , Vamsi K. Paruchuri , Sufi Zafar
发明人： Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Leland Chang , Christopher P. D'Emic , Martin M. Frank , Evgeni Gusev , Jin-Ping Han , Rajarao Jammy , Vamsi K. Paruchuri , Sufi Zafar
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L21/823857 , H01L21/28167 , H01L21/28194 , H01L29/51 , H01L29/513 , H01L29/78
摘要： A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.
摘要翻译：提供了一种半导体结构，特别是栅极堆叠，其中通过向栅极电介质材料引入电荷密度的固定空间分布来控制其阈值电压的场效应晶体管（FET）及其形成方法。公开了nFET和/或pFET结构。根据本发明，栅极堆叠或FET的电荷密度的固定空间分布表示占空间的电荷密度，其在器件操作条件下作为时间的函数保持基本上恒定，并且至少在电介质材料内的一个位置，或其与沟道，栅电极，间隔物或器件的任何其它结构元件的界面。

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