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1. 发明授权

US08557670B1 SOI lateral bipolar junction transistor having a wide band gap emitter contact 有权
标题翻译：具有宽带隙发射极接触的SOI横向双极结型晶体管
公开(公告)号：US08557670B1
公开(公告)日：2013-10-15
申请号：US13605253
申请日：2012-09-06
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/8222
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。在堆叠周围形成介电隔离件。执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

2. 发明申请

US20130256757A1 SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT 审中-公开
标题翻译：具有宽带带隙发射体接触的SOI侧向双极晶体管
公开(公告)号：US20130256757A1
公开(公告)日：2013-10-03
申请号：US13433537
申请日：2012-03-29
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。在堆叠周围形成介电隔离件。执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

3. 发明授权

US08586441B1 Germanium lateral bipolar junction transistor 有权
标题翻译：锗横向双极结晶体管
公开(公告)号：US08586441B1
公开(公告)日：2013-11-19
申请号：US13611606
申请日：2012-09-12
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/331
CPC分类号： H01L29/6625 , H01L29/161 , H01L29/735
摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.
摘要翻译：使用绝缘体上的锗（GOI）衬底形成锗横向双极结型晶体管（BJT）。在GOI衬底的锗层的顶表面上沉积硅钝化层。随后形成浅沟槽隔离结构，非本征基区结构和基底间隔物。通过离子注入在锗层内形成锗发射极区，锗基区和锗集电极区。在硅钝化层中形成硅发射极区域，硅基区域和硅集电极区域。在可选地形成发射极接触区域和集电极接触区域之后，可以形成金属半导体合金区域。在硅基区和锗基区之间以及硅发射极区和锗发射极区之间提供少量载流子的宽间隙接触。

4. 发明授权

US08558282B1 Germanium lateral bipolar junction transistor 有权
公开(公告)号：US08558282B1
公开(公告)日：2013-10-15
申请号：US13607672
申请日：2012-09-08
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/331
CPC分类号： H01L29/6625 , H01L29/161 , H01L29/735
摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.

5. 发明申请

US20130260526A1 SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT 有权
公开(公告)号：US20130260526A1
公开(公告)日：2013-10-03
申请号：US13605253
申请日：2012-09-06
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/8222
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.

6. 发明授权

US08421191B2 Monolayer dopant embedded stressor for advanced CMOS 有权
标题翻译：单层掺杂剂嵌入式应力器用于高级CMOS
公开(公告)号：US08421191B2
公开(公告)日：2013-04-16
申请号：US13533499
申请日：2012-06-26
申请人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
IPC分类号： H01L31/117
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.
摘要翻译：公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

7. 发明申请

US20130032883A1 FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING 有权
公开(公告)号：US20130032883A1
公开(公告)日：2013-02-07
申请号：US13198255
申请日：2011-08-04
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L29/78 , H01L21/336 , H01L21/24
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.

8. 发明申请

US20110062518A1 finFETS AND METHODS OF MAKING SAME 有权
公开(公告)号：US20110062518A1
公开(公告)日：2011-03-17
申请号：US12561606
申请日：2009-09-17
申请人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
发明人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

9. 发明授权

US07989298B1 Transistor having V-shaped embedded stressor 有权
标题翻译：具有V形嵌入应力的晶体管
公开(公告)号：US07989298B1
公开(公告)日：2011-08-02
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

10. 发明申请

US20110183486A1 TRANSISTOR HAVING V-SHAPED EMBEDDED STRESSOR 有权
标题翻译：具有V形嵌入式应力的晶体管
公开(公告)号：US20110183486A1
公开(公告)日：2011-07-28
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

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