专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07132182B2 Method and apparatus for electrochemical compression and expansion of hydrogen in a fuel cell system 有权
公开(公告)号：US07132182B2
公开(公告)日：2006-11-07
申请号：US10213798
申请日：2002-08-07
申请人： James F. McElroy , Arne W. Ballantine , Richard L. Chartrand
发明人： James F. McElroy , Arne W. Ballantine , Richard L. Chartrand
IPC分类号： H01M8/04
CPC分类号： H01M8/0618 , C01B3/503 , C01B2203/0405 , C01B2203/0475 , H01M8/04089 , H01M8/04097 , H01M8/04111 , H01M8/04126 , H01M8/04201 , H01M8/0681 , H01M2008/1095 , H01M2250/20 , Y02P30/30 , Y02T90/32
摘要： The invention relates to fuel cell systems and associated methods of operation where an electrochemical cell such as a fuel cell is used as an electrochemical hydrogen separator to separate hydrogen from a process stream (e.g., reformate or synthesis gas), or as an electrochemical hydrogen expander to inject hydrogen into a process stream. In one aspect, the invention provides a method of operating a fuel cell system, including the following steps: flowing hydrogen from a hydrogen supply conduit through a fuel cell to provide an electric current to a load coupled to the fuel cell; actuating an electrochemical hydrogen separator in a first mode of operation of the system to transfer hydrogen from the hydrogen supply conduit to a hydrogen storage vessel; and actuating an electrochemical hydrogen expander in a second mode of operation of the system to transfer hydrogen from the hydrogen storage vessel to the fuel cell.

2. 发明授权

US06939771B2 Discontinuous dielectric interface for bipolar transistors 失效
标题翻译：双极晶体管的不连续介质接口
公开(公告)号：US06939771B2
公开(公告)日：2005-09-06
申请号：US10653925
申请日：2003-09-04
申请人： Arne W. Ballantine , Douglas D. Coolbaugh , Jeffrey Gilbert , Joseph R. Greco , Glenn R. Miller
发明人： Arne W. Ballantine , Douglas D. Coolbaugh , Jeffrey Gilbert , Joseph R. Greco , Glenn R. Miller
IPC分类号： H01L29/73 , H01L21/314 , H01L21/318 , H01L21/328 , H01L21/331 , H01L29/08
CPC分类号： H01L29/66272 , H01L21/3144 , H01L21/3185 , H01L29/0804 , H01L29/0895
摘要： A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
摘要翻译：一种在半导体材料的两个区域之间形成至少一个界面区域的方法。在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。

3. 发明授权

US06759260B2 Metal oxide temperature monitor 失效
标题翻译：金属氧化物温度监测仪
公开(公告)号：US06759260B2
公开(公告)日：2004-07-06
申请号：US10421986
申请日：2003-04-23
申请人： Arne W. Ballantine , Edward C. Cooney, III , Jeffrey D. Gilbert , Robert G. Miller , Amy L. Myrick , Ronald A. Warren
发明人： Arne W. Ballantine , Edward C. Cooney, III , Jeffrey D. Gilbert , Robert G. Miller , Amy L. Myrick , Ronald A. Warren
IPC分类号： H01L2166
CPC分类号： H01L21/67248 , H01L21/67098
摘要： A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600° C., wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600° C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface. In addition, the monitor may be reconditioned for repeated use by heating the monitor in a hydrogen ambient environment to convert the oxide layer to unoxidized copper. Additionally, the oxide layer has a color that is a function of the oxide layer thickness, where the color may be used to estimate the temperature at which the wafer was heated in the ambient oxygen atmosphere.
摘要翻译：一种用于监测加热室中温度范围为200至600℃的温度和温度分布的方法和相关结构，其中加热室可用于制造半导体器件。铜层沉积在半导体晶片的表面上。接下来，将晶片在环境氧气氛中加热到200-600℃的温度。晶片的加热使生成氧化物层的铜层的一部分氧化。加热后，去除晶片，并在晶片表面上的点测量薄层电阻。由于局部薄层电阻是氧化物层的局部厚度的函数，所以晶片表面上的薄层电阻的空间分布反映了在晶片加热期间晶片温度跨晶片表面的分布。测量的薄层电阻的空间分布可以用于重新调整输入到另一晶片的热空间分布，以便在另一晶片的表面上实现更均匀的温度。此外，可以通过在氢环境环境中加热监测器来重新使用监视器以重新使用以将氧化物层转化为未氧化的铜。此外，氧化物层具有作为氧化物层厚度的函数的颜色，其中可以使用颜色来估计晶片在环境氧气氛中被加热的温度。

4. 发明授权

US06703283B1 Discontinuous dielectric interface for bipolar transistors 有权
标题翻译：双极晶体管的不连续介质接口
公开(公告)号：US06703283B1
公开(公告)日：2004-03-09
申请号：US09244958
申请日：1999-02-04
申请人： Arne W. Ballantine , Douglas D. Coolbaugh , Jeffrey Gilbert , Joseph R. Greco , Glenn R. Miller
发明人： Arne W. Ballantine , Douglas D. Coolbaugh , Jeffrey Gilbert , Joseph R. Greco , Glenn R. Miller
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L21/3144 , H01L21/3185 , H01L29/0804 , H01L29/0895
摘要： A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.
摘要翻译：一种在半导体材料的两个区域之间形成至少一个界面区域的方法。在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。

5. 发明授权

US06580140B1 Metal oxide temperature monitor 失效
公开(公告)号：US06580140B1
公开(公告)日：2003-06-17
申请号：US09665584
申请日：2000-09-18
申请人： Arne W. Ballantine , Edward C. Cooney, III , Jeffrey D. Gilbert , Robert G. Miller , Amy L. Myrick , Ronald A. Warren
发明人： Arne W. Ballantine , Edward C. Cooney, III , Jeffrey D. Gilbert , Robert G. Miller , Amy L. Myrick , Ronald A. Warren
IPC分类号： H01L31058
CPC分类号： H01L21/67248 , H01L21/67098
摘要： A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600° C., wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600° C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface. In addition, the monitor may be reconditioned for repeated use by heating the monitor in a hydrogen ambient environment to convert the oxide layer to unoxidized copper. Additionally, the oxide layer has a color that is a function of the oxide layer thickness, where the color may be used to estimate the temperature at which the wafer was heated in the ambient oxygen atmosphere.

6. 发明授权

US06498462B2 Generator control system to accommodate a decrease in a power grid voltage 有权
公开(公告)号：US06498462B2
公开(公告)日：2002-12-24
申请号：US09777156
申请日：2001-02-05
申请人： Arne W. Ballantine , Mark R. Torpey
发明人： Arne W. Ballantine , Mark R. Torpey
IPC分类号： H02P904
CPC分类号： H02J3/38 , H02J2003/388 , Y10T307/724
摘要： A system includes a generator and a circuit. The generator is coupled to provide power to a power grid. The circuit is coupled to the generator and is adapted to use a scheme to detect a shut down of the power grid and prevent the generator from providing power to the power grid in response to the detection of the shut down of the power grid. The circuit is also adapted to receive an indication to modify the scheme and modify the scheme based on the indication.

7. 发明授权

US06489663B2 Spiral inductor semiconducting device with grounding strips and conducting vias 有权
公开(公告)号：US06489663B2
公开(公告)日：2002-12-03
申请号：US09753284
申请日：2001-01-02
申请人： Arne W. Ballantine , Robert A. Groves , Michael B. Rice , Anthony K. Stamper
发明人： Arne W. Ballantine , Robert A. Groves , Michael B. Rice , Anthony K. Stamper
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： An integrated semiconducting device comprises a semiconducting substrate, a plurality of grounding strips disposed above the substrate in a lower metal level of the semiconducting device, an inductor positioned in an upper metal level of the semiconducting device, and a plurality of conducting vias connected to and extending away from the grounding strips towards the inductor. The inductor, conducting via, ground strips structure forms a Faraday cage that acts as a shield against electromagnetic radiation. The number and placement of the conductive vias are adjustable and can be optimized based on the relative importance of maximizing the quality factor Q of the inductor or minimizing the capacitance between the inductor and ground.

8. 发明授权

US06448590B1 Multiple threshold voltage FET using multiple work-function gate materials 失效
标题翻译：多阈值电压FET采用多功能栅极材料
公开(公告)号：US06448590B1
公开(公告)日：2002-09-10
申请号：US09695199
申请日：2000-10-24
申请人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
发明人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
IPC分类号： H01L2710
CPC分类号： H01L29/4916 , H01L21/82345 , H01L29/4238 , H01L29/495 , H01L29/4966 , H01L29/66666 , H01L29/7827
摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
摘要翻译：通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。通过组合多个功能门极材料来开发多个阈值电压。栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。开发了用于多阈值电压设计的图案化线性阵列实施例。形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。栅极材料被布置成彼此靠近以适应小栅极长度设计。

9. 发明授权

US06441396B1 In-line electrical monitor for measuring mechanical stress at the device level on a semiconductor wafer 失效
标题翻译：用于测量半导体晶片上器件级别的机械应力的在线电气监控器
公开(公告)号：US06441396B1
公开(公告)日：2002-08-27
申请号：US09695038
申请日：2000-10-24
申请人： Edward D. Adams , Arne W. Ballantine , Richard S. Kontra , Alain Loiseau , James A. Slinkman
发明人： Edward D. Adams , Arne W. Ballantine , Richard S. Kontra , Alain Loiseau , James A. Slinkman
IPC分类号： H01L2358
CPC分类号： H01L23/544 , G01N2203/0016 , G01N2203/0025 , G01N2203/0286 , G01N2203/0617 , H01L21/67288 , H01L22/12 , H01L22/34 , H01L29/7842 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method is presented for measuring and monitoring the mechanical stress at the device level which occurs intrinsically during the fabrication process or which is induced via extrinsic means. The method applies the fact that the current-voltage (I-V) characteristics of a diode change as the diode is subjected to mechanical stress. The method is applicable to monitoring stress at the microscopic and device levels at various stages in the semiconductor wafer fabrication process. Apparatus for implementing the method is also presented.
摘要翻译：提出了一种用于测量和监测在制造过程中本质上发生的或通过外在手段诱发的器件级别的机械应力的方法。该方法应用二极管受到机械应力时二极管的电流 - 电压（I-V）特性改变的事实。该方法适用于在半导体晶片制造过程的各个阶段监测微观和器件级的应力。还介绍了实现该方法的装置。

10. 发明授权

US06339018B1 Silicide block bounded device 失效
标题翻译：硅化物块有界装置
公开(公告)号：US06339018B1
公开(公告)日：2002-01-15
申请号：US09521719
申请日：2000-03-09
申请人： Arne W. Ballantine , Terence B. Hook
发明人： Arne W. Ballantine , Terence B. Hook
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L29/665
摘要： A method and structure for preventing device leakage. The method and structure includes forming a blocking layer of preferably nitride over a junction between a source/drain region and a shallow trench isolation. A silicide is then formed over a landed area of the source/drain region but is blocked by the blocking layer from forming over the junction between the source/drain region and the shallow trench isolation. This prevents device leakage at this location.
摘要翻译：一种防止设备泄漏的方法和结构。该方法和结构包括在源极/漏极区域和浅沟槽隔离之间的结上形成优选氮化物的阻挡层。然后在源极/漏极区域的着陆区域上形成硅化物，但是被阻挡层阻挡在源极/漏极区域和浅沟槽隔离之间的结上形成。这可以防止在此位置的设备泄漏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式