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1. 发明授权

US07816224B2 Method for fabricating an ultra thin silicon on insulator 有权
标题翻译：用于制造绝缘体上的超薄硅的方法
公开(公告)号：US07816224B2
公开(公告)日：2010-10-19
申请号：US12042936
申请日：2008-03-05
申请人： Kevin K. Chan , Jakub Kedzierski , Raymond M. Sicina
发明人： Kevin K. Chan , Jakub Kedzierski , Raymond M. Sicina
IPC分类号： H01L21/76
CPC分类号： H01L29/66628 , H01L21/7624 , H01L29/66772 , H01L29/78654
摘要： In one embodiment, the invention is a method for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
摘要翻译：在一个实施例中，本发明是用于制造绝缘体上的超薄硅的方法。用于制造绝缘体上的超薄硅的方法的一个实施例包括提供硅层，在第一温度下使硅层与至少一种反应气体饱和，第一温度足够低以基本上防止发生任何涉及反应气体，并将第一温度升至第二温度，第二温度大约为反应气体的解离温度。

2. 发明授权

US07859060B2 Ultra thin silicon on insulator 有权
标题翻译：超薄硅绝缘体
公开(公告)号：US07859060B2
公开(公告)日：2010-12-28
申请号：US12535398
申请日：2009-08-04
申请人： Kevin K. Chan , Jakub Kedzierski , Raymond M. Sicina
发明人： Kevin K. Chan , Jakub Kedzierski , Raymond M. Sicina
IPC分类号： H01L29/94
CPC分类号： H01L29/66628 , H01L21/7624 , H01L29/66772 , H01L29/78654
摘要： In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.
摘要翻译：在一个实施例中，本发明是用于制造绝缘体上的超薄硅的方法和装置。用于制造绝缘体上的超薄硅的方法的一个实施例包括提供硅层，在第一温度下使硅层与至少一种反应气体饱和，第一温度足够低以基本上防止发生任何涉及反应气体，并将第一温度升至第二温度，第二温度大约为反应气体的解离温度。

3. 发明授权

US06350321B1 UHV horizontal hot wall cluster CVD/growth design 失效
标题翻译：特高压水平热壁簇CVD /生长设计
公开(公告)号：US06350321B1
公开(公告)日：2002-02-26
申请号：US09207353
申请日：1998-12-08
申请人： Kevin K. Chan , Christopher P. D'Emic , Raymond M. Sicina , Paul M. Kozlowski , Margaret Manny , Sandip Tiwari
发明人： Kevin K. Chan , Christopher P. D'Emic , Raymond M. Sicina , Paul M. Kozlowski , Margaret Manny , Sandip Tiwari
IPC分类号： C23C1600
CPC分类号： H01L21/67225 , C23C14/56
摘要： A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H2O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace. Furthermore, before any wafers are placed into the transfer chamber, they are loaded into a load/unload chamber, which is the sole connection to the ambient air, to be purged and pumped so as to minimize particles and contamination.
摘要翻译：簇系统控制在硅衬底上沉积或生长的膜的界面性质。该系统包括多个水平石英腔或管，每个水平的石英腔或管可以容纳大量的晶片，传送室和装载/卸载室。可以在不同环境空气的情况下，在不同的管中顺序执行若干工艺步骤。传输室连接它们，并允许晶片在绝对控制的特高压环境中从一个管到另一个管输送，将任何污染（例如H 2 O）限制到小于单层。此外，每个管可以泵送到特高压压力状态，以避免管之间的进一步交叉污染或产生颗粒。由于某些过程需要升高的温度，因此将所有晶片垂直放置在石英舟上，以防止垂直炉中出现任何晶片下垂。此外，在将任何晶片放入转移室之前，它们被装载到与环境空气的唯一连接的装载/卸载室中，以被清除和泵送，以使颗粒和污染物最小化。

4. 发明授权

US08716096B2 Self-aligned emitter-base in advanced BiCMOS technology 失效
标题翻译：先进的BiCMOS技术中的自对准发射极基极
公开(公告)号：US08716096B2
公开(公告)日：2014-05-06
申请号：US13323977
申请日：2011-12-13
申请人： Kevin K. Chan , David L. Harame , Russell T. Herrin , Qizhi Liu
发明人： Kevin K. Chan , David L. Harame , Russell T. Herrin , Qizhi Liu
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/737 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7371
摘要： A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.
摘要翻译：公开了一种自对准双极晶体管及其制造方法。在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。形成第一开口，暴露外部基底的表面的一部分。在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。在第一和第二槽中的每一个中的暴露的本征和/或非本征基极层上选择性地生长硅层条纹，基本上填充相应的槽。

5. 发明授权

US08603883B2 Interface control in a bipolar junction transistor 失效
标题翻译：双极结晶体管中的接口控制
公开(公告)号：US08603883B2
公开(公告)日：2013-12-10
申请号：US13297464
申请日：2011-11-16
申请人： Kevin K. Chan , Peng Cheng , Qizhi Liu , Ljubo Radic
发明人： Kevin K. Chan , Peng Cheng , Qizhi Liu , Ljubo Radic
IPC分类号： H01L21/331
CPC分类号： H01L29/73 , G06F17/5045 , H01L29/1004 , H01L29/66272 , H01L29/7371
摘要： Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.
摘要翻译：制造双极结型晶体管，双极结型晶体管以及双极结型晶体管的设计结构的方法。本征基底层的第一部分被掩蔽，同时蚀刻本征基底层的第二部分。作为掩蔽的结果，本征基底层的第二部分比本征基底层的第一部分薄。在与本征基层的第一和第二部分分别的接触关系中形成发射极和非本征基层。

6. 发明申请

US20130119442A1 JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY 有权
标题翻译：具有选择性外延形成的上升源和漏区的连接场效应晶体管
公开(公告)号：US20130119442A1
公开(公告)日：2013-05-16
申请号：US13294731
申请日：2011-11-11
申请人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： Kevin K. Chan , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L21/337 , G06F17/50 , H01L29/808
CPC分类号： H01L29/8086 , G06F17/5045 , H01L27/0623 , H01L29/0817 , H01L29/0826 , H01L29/1004 , H01L29/1058 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66893 , H01L29/66901 , H01L29/732 , H01L29/7375 , H01L29/808
摘要： Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.
摘要翻译：结型场效应晶体管，用于制造结型场效应晶体管的方法，以及结型场效应晶体管的设计结构。结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

7. 发明申请

US20120289018A1 SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR 有权
标题翻译： SOI SiGe-BASE横向双极晶体管晶体管
公开(公告)号：US20120289018A1
公开(公告)日：2012-11-15
申请号：US13556372
申请日：2012-07-24
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L21/331
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

8. 发明授权

US08198673B2 Asymmetric epitaxy and application thereof 有权
标题翻译：不对称外延及其应用
公开(公告)号：US08198673B2
公开(公告)日：2012-06-12
申请号：US13080702
申请日：2011-04-06
申请人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
发明人： Haizhou Yin , Xinhui Wang , Kevin K. Chan , Zhibin Ren
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。该方法包括在半导体衬底的顶部上形成栅极结构，该栅极结构包括一个栅极叠层和邻近该栅极叠层的侧壁的间隔物，并具有与第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。还提供了由此形成的半导体结构。

9. 发明授权

US08035141B2 Bi-layer nFET embedded stressor element and integration to enhance drive current 有权
标题翻译：双层nFET嵌入式应力元件并集成增强驱动电流
公开(公告)号：US08035141B2
公开(公告)日：2011-10-11
申请号：US12607104
申请日：2009-10-28
申请人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834 , Y10S257/90 , Y10S257/902 , Y10S257/903
摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.
摘要翻译：公开了一种包括双层nFET嵌入式应力元件的半导体结构。双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

10. 发明授权

US07989298B1 Transistor having V-shaped embedded stressor 有权
标题翻译：具有V形嵌入应力的晶体管
公开(公告)号：US07989298B1
公开(公告)日：2011-08-02
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

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