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1. 发明授权

US06821910B2 Spatially programmable microelectronics process equipment using segmented gas injection showerhead with exhaust gas recirculation 有权
公开(公告)号：US06821910B2
公开(公告)日：2004-11-23
申请号：US10333784
申请日：2003-01-24
申请人： Raymond A. Adomaitis , John N. Kidder, Jr. , Gary W. Rubloff
发明人： Raymond A. Adomaitis , John N. Kidder, Jr. , Gary W. Rubloff
IPC分类号： H01L21469
CPC分类号： C23C16/44 , C23C16/4412 , C23C16/455 , C23C16/45561 , C23C16/45565 , C23C16/45574 , C23C16/52 , H01L21/67017
摘要： A multizone, segmented showerhead provides a gas impingement flux distribution which is controllable in two lateral dimensions to achieve programmable uniformity in chemical vapor deposition, in plasma deposition and etching and other processes. Recirculation (pumping) of exhaust gases back through the showerhead reduces intersegment mixing to achieve a high degree of spatial control of the process. This spatial control of the impinging gas flux distribution assures that uniformity can be achieved at process design points selected to optimize materials performance. Spatial control also permits rapid experimentation by enabling the introduction of intentional nonuniformities so that combinatorial data from across the wafer/substrate provides results of simultaneous experiments at different process design points. This ability is useful for process tuning and optimization in manufacturing or for rapid materials and process discovery and optimization in research and development.

2. 发明授权

US06780793B2 Production method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06780793B2
公开(公告)日：2004-08-24
申请号：US09955810
申请日：2001-09-19
申请人： Yoshiyuki Tanaka , Yoshiyuki Enomoto , Masaki Saito
发明人： Yoshiyuki Tanaka , Yoshiyuki Enomoto , Masaki Saito
IPC分类号： H01L21469
CPC分类号： H01L21/02164 , H01L21/02131 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/0234 , H01L21/31629 , H01L21/76801 , H01L21/76819 , H01L21/76837
摘要： An improved method for producing a semiconductor device with a fluorine-doped silicon oxide interlayer insulating film. In one embodiment, the fluorine-doped silicon oxide layer (FSG layer) is formed in a process chamber. Thereafter, a silicon oxide layer is formed in the same process chamber over the FSG layer at a higher temperature than the FSG layer formation temperature. In another embodiment, after the FSG layer is formed, a surface layer of the FSG layer is selectively sputtered away before the silicon oxide layer is formed.
摘要翻译：一种用于制造具有氟掺杂氧化硅层间绝缘膜的半导体器件的改进方法。在一个实施例中，在处理室中形成氟掺杂氧化硅层（FSG层）。此后，在与FSG层形成温度相比更高的温度下，在FSG层上的相同处理室中形成氧化硅层。在另一个实施例中，在形成FSG层之后，在形成氧化硅层之前，FSG层的表面层被选择性地溅射掉。

3. 发明授权

US06709991B1 Method of fabricating semiconductor device with capacitor 失效
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US06709991B1
公开(公告)日：2004-03-23
申请号：US09084578
申请日：1998-05-26
申请人： Jun Kawahara , Shinobu Saito , Yukihiko Maejima , Yoshihiro Hayashi
发明人： Jun Kawahara , Shinobu Saito , Yukihiko Maejima , Yoshihiro Hayashi
IPC分类号： H01L21469
CPC分类号： H01L28/57 , H01L21/02164 , H01L21/0217 , H01L21/02216 , H01L21/02219 , H01L21/02271 , H01L21/31612 , H01L21/76801 , H01L21/76802
摘要： A fabrication method of a semiconductor device with a capacitor is provided, which prevents leakage current from increasing and dielectric breakdown resistance from decreasing during a CVD or dry etching process for forming an insulating film to cover the capacitor. In this method, a lower electrode of a capacitor is formed on a first insulating film. The first insulating film is typically formed on or over a semiconductor substrate. A dielectric film of the capacitor is formed on the lower electrode to be overlapped therewith. An upper electrode of the capacitor is formed on the dielectric film to be overlapped therewith. A second insulating film is formed to cover the capacitor by a thermal CVD process in an atmosphere containing no plasma at a substrate temperature in which hydrogen is prevented from being activated due to heat. A source material of the second insulating film has a property that no hydrogen is generated in the atmosphere through decomposition of the source material during the thermal CVD process.
摘要翻译：提供了具有电容器的半导体器件的制造方法，其防止了在用于形成绝缘膜以覆盖电容器的CVD或干蚀刻工艺期间泄漏电流增加和绝缘击穿电阻降低。在该方法中，在第一绝缘膜上形成电容器的下电极。第一绝缘膜通常形成在半导体衬底上或上方。电容器的电介质膜形成在下电极上以与其重叠。电容器的上电极形成在电介质膜上以与其重叠。形成第二绝缘膜，通过热CVD法在不防止由于热而被活化的基板温度下的不含等离子体的气氛中覆盖电容器。第二绝缘膜的源材料具有通过在热CVD工艺期间源材料分解而在大气中不产生氢的性质。

4. 发明授权

US06709990B2 Method for fabrication of a high capacitance interpoly dielectric 有权
标题翻译：高电容互聚电介质的制造方法
公开(公告)号：US06709990B2
公开(公告)日：2004-03-23
申请号：US10267354
申请日：2002-10-09
申请人： Mark A. Good , Amit S. Kelkar
发明人： Mark A. Good , Amit S. Kelkar
IPC分类号： H01L21469
CPC分类号： H01L21/02326 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/3144
摘要： A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.
摘要翻译：一种制造具有薄氮化硅层的二氧化硅/氮化硅/二氧化硅（ONO）层叠复合体的方法，用于提供高电容互聚电介质结构。在ONO复合材料的形成中，在诸如多晶硅的衬底上形成底部二氧化硅层。在二氧化硅层上形成氮化硅层，通过氧化而变薄。氮化硅膜的氧化通过产生二氧化硅层的反应消耗一些氮化硅。用氢氟酸稀释液除去该二氧化硅层。当在氮化硅层上形成顶部二氧化硅层时，氮化硅层又被再次氧化而变薄。在氮化硅上沉积第二层多晶硅，形成多晶硅间电介质。

5. 发明授权

US06699799B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US06699799B2
公开(公告)日：2004-03-02
申请号：US10134747
申请日：2002-04-30
申请人： Dong-Ho Ahn , Soo-Jin Hong , Jung-Il Lee , Kyung-won Park
发明人： Dong-Ho Ahn , Soo-Jin Hong , Jung-Il Lee , Kyung-won Park
IPC分类号： H01L21469
CPC分类号： H01L21/0234 , H01L21/02134 , H01L21/02164 , H01L21/02282 , H01L21/02348 , H01L21/31053 , H01L21/316 , H01L21/76229
摘要： A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.
摘要翻译：一种形成半导体器件的方法包括：在涂覆SOG层之前，在半导体衬底上保形地层叠衬垫，然后固化SOG层，优选在1000℃或更高温度下形成的氧自由基的环境中固化供应氧气和氢气。氧自由基优选通过将紫外线照射到臭氧或形成氧等离子体来形成。 SOG层优选由可以促进SOG层转化为氧化硅层的基于聚硅氮烷的材料制成。

6. 发明授权

US06664201B2 Method of manufacturing anti-reflection layer 有权
公开(公告)号：US06664201B2
公开(公告)日：2003-12-16
申请号：US10010865
申请日：2001-12-05
申请人： Jing-Horng Gau , Shuenn-Jeng Chen
发明人： Jing-Horng Gau , Shuenn-Jeng Chen
IPC分类号： H01L21469
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/3145
摘要： An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

7. 发明授权

US06649541B1 Method for preventing or reducing delamination of deposited insulating layers 失效
标题翻译：防止或减少沉积绝缘层分层的方法
公开(公告)号：US06649541B1
公开(公告)日：2003-11-18
申请号：US09920490
申请日：2001-08-01
申请人： Allen Lewis Evans , David E. Brown , Michael J. Satterfield , Arturo N. Morosoff
发明人： Allen Lewis Evans , David E. Brown , Michael J. Satterfield , Arturo N. Morosoff
IPC分类号： H01L21469
CPC分类号： H01L21/02274 , C23C16/402 , H01L21/02164 , H01L21/02211 , H01L21/31612 , H01L21/76801 , H01L21/76829
摘要： The method disclosed herein provides a semiconducting substrate, positioning the substrate in a high density plasma process chamber, and forming a layer of silicon-rich silicon dioxide above the substrate using a high density plasma process with an oxygen/silane flowrate ratio that is less than or equal to 0.625. In another embodiment, the method provides a semiconducting substrate having a partially formed integrated circuit device formed thereabove, the integrated circuit device having a plurality of conductive interconnections, e.g., conductive lines or conductive plugs, formed thereon, and positioning the substrate in a high density plasma process chamber. The method further includes forming a first layer of silicon dioxide between the plurality of conductive interconnections using a high density plasma process with an oxygen/silane flowrate ratio less than 1.0, and forming a layer of insulating material above the first layer between the conductive interconnections. In another aspect of the present invention, an integrated circuit device has of a plurality of conductive interconnections, e.g., conductive lines, formed above a semiconducting substrate, a layer of silicon dioxide having a silicon content ranging from approximately 50-75 weight percent positioned between the conductive inter-connections, and a layer of insulating material positioned above the layer of silicon dioxide between the conductive interconnections.
摘要翻译：本文公开的方法提供半导体衬底，将衬底定位在高密度等离子体处理室中，并且使用氧/硅烷流量比小于等于的高密度等离子体工艺在衬底上形成富硅二氧化硅层或等于0.625。在另一个实施例中，该方法提供了一种半导体衬底，其具有形成在其上面的部分形成的集成电路器件，该集成电路器件具有多个导电互连，例如在其上形成的导电线或导电插塞，并且将衬底以高密度等离子体处理室。该方法还包括使用氧/硅烷流量比小于1.0的高密度等离子体工艺在多个导电互连之间形成第二层二氧化硅，以及在导电互连之间在第一层之上形成一层绝缘材料。在本发明的另一方面，集成电路器件具有形成在半导体衬底上方的多个导电互连（例如，导线），二氧化硅层的硅含量范围为约50-75重量％导电互连，以及位于导电互连之间的二氧化硅层之上的绝缘材料层。

8. 发明授权

US06642145B1 Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers 有权
标题翻译：制造在互连和层间电介质层之间形成的介电扩散阻挡层的集成电路的制造方法
公开(公告)号：US06642145B1
公开(公告)日：2003-11-04
申请号：US10226520
申请日：2002-08-22
申请人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
发明人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
IPC分类号： H01L21469
CPC分类号： H01L23/5329 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76841 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。形成在半导体衬底上的电介质层具有设置在其中的开口。电介质层是能够改变为阻挡介电材料的非阻挡介电材料。开口周围的电介质层变成阻挡介电材料，并且沉积导体芯材以填充开口。处理导体芯以形成用于集成电路的通道。

9. 发明授权

US06602801B2 Method for forming a region of low dielectric constant nanoporous material 有权
标题翻译：形成低介电常数纳米多孔材料区域的方法
公开(公告)号：US06602801B2
公开(公告)日：2003-08-05
申请号：US10012294
申请日：2001-11-13
申请人： Siew Yong Kong , Alex See , Simon Chooi , Gautam Sarkar
发明人： Siew Yong Kong , Alex See , Simon Chooi , Gautam Sarkar
IPC分类号： H01L21469
CPC分类号： H01L21/02126 , H01L21/02118 , H01L21/02203 , H01L21/02282 , H01L21/31695 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , Y10S977/827 , H01L2924/00
摘要： A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of combining a plurality of materials to form a solution. In the present embodiment, the plurality of materials comprising a low dielectric constant material, a pore generator material, and a solvent. In this embodiment, the present method then applies the solution to a surface above which it is desired to form the region of low dielectric constant nanoporous material. Next, the present embodiment subjects the solution, which has been applied to the surface, to a thermal process such that a region of low dielectric constant nanoporous material is formed above the surface.
摘要翻译：公开了一种形成低介电常数纳米多孔材料区域的方法。在一个实施例中，本方法包括组合多种材料以形成溶液的步骤。在本实施例中，包括低介电常数材料，孔发生器材料和溶剂的多种材料。在本实施例中，本方法然后将溶液施加到希望形成低介电常数纳米多孔材料区域的表面上。接下来，本实施例将已经施加到表面的溶液作为热处理，使得在表面上方形成低介电常数纳米多孔材料的区域。

10. 发明授权

US06562734B2 Method of filling gaps on a semiconductor wafer 有权
公开(公告)号：US06562734B2
公开(公告)日：2003-05-13
申请号：US09954414
申请日：2001-09-17
申请人： Markus Kirchhoff
发明人： Markus Kirchhoff
IPC分类号： H01L21469
CPC分类号： H01L21/76837 , H01L21/31604 , H01L21/3185 , H01L21/76232
摘要： A method of filling gaps on a semiconductor wafer with a dielectric material employs a plasma enhanced chemical vapor deposition (PECVD) process with a temperature in the range of 500 to 700° C. As a result of the deposition process, gaps resulting from e.g. shallow trench isolation or premetal dielectric techniques are filled homogeneously without any voids. The deposition may be improved by applying two radio frequency signals with different frequencies.

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