专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09059321B2 Buried channel field-effect transistors 有权
标题翻译：埋地通道场效应晶体管
公开(公告)号：US09059321B2
公开(公告)日：2015-06-16
申请号：US13470620
申请日：2012-05-14
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L21/338 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/10 , H01L29/786 , H01L29/78 , H01L21/8238 , H01L29/51
CPC分类号： H01L29/0642 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0692 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/78687 , H01L29/78696
摘要： Methods for forming a buried-channel field-effect transistor include doping source and drain regions on a substrate with a dopant having a first type; forming a doped shielding layer on the substrate in a channel region having a second doping type opposite the first type to displace a conducting channel away from a gate-interface region; forming a gate dielectric over the doped shielding layer; and forming a gate on the gate dielectric.
摘要翻译：用于形成掩埋沟道场效应晶体管的方法包括在具有第一类型的掺杂剂的衬底上掺杂源区和漏区; 在具有与第一类型相反的第二掺杂类型的沟道区域中的衬底上形成掺杂的屏蔽层，以使导电沟道偏离栅极 - 界面区域; 在所述掺杂屏蔽层上形成栅极电介质; 并在栅极电介质上形成栅极。

2. 发明授权

US08928096B2 Buried-channel field-effect transistors 有权
标题翻译：掩埋通道场效应晶体管
公开(公告)号：US08928096B2
公开(公告)日：2015-01-06
申请号：US13474949
申请日：2012-05-18
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L21/02
CPC分类号： H01L29/0642 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0692 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/78687 , H01L29/78696
摘要： A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer.
摘要翻译：掩埋沟道场效应晶体管包括形成在基板上的半导体层。半导体层包括掺杂的源极和漏极区域以及未掺杂的沟道区域。所述晶体管还包括形成在所述沟道区上并部分地与所述源极和漏极区重叠的栅极电介质; 形成在栅极电介质上的栅极; 以及在栅极电介质和半导体层之间的掺杂屏蔽层。

3. 发明授权

US08927380B2 SOI bipolar junction transistor with substrate bias voltages 有权
公开(公告)号：US08927380B2
公开(公告)日：2015-01-06
申请号：US13369261
申请日：2012-02-08
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66234 , H01L21/761 , H01L27/082 , H01L27/1203 , H01L29/73
摘要： A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.

4. 发明授权

US08803233B2 Junctionless transistor 有权
标题翻译：无结晶体晶体管
公开(公告)号：US08803233B2
公开(公告)日：2014-08-12
申请号：US13242861
申请日：2011-09-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L29/778
CPC分类号： H01L21/823807 , H01L27/0922 , H01L27/1203 , H01L29/78654 , H01L29/78696
摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.
摘要翻译：晶体管包括半导体层，并且在半导体层上形成栅极电介质。栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。该渐变掺杂剂区域的掺杂浓度逐渐降低。晶体管还包括与有源区相邻的源区和漏区。源极和漏极区域和有源区域具有相同的导电类型。

5. 发明授权

US08664721B2 FET with FUSI gate and reduced source/drain contact resistance 有权
标题翻译：具有FUSI栅极的FET和降低的源极/漏极接触电阻
公开(公告)号：US08664721B2
公开(公告)日：2014-03-04
申请号：US13569741
申请日：2012-08-08
申请人： Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhen Zhang
IPC分类号： H01L27/12 , H01L29/45
CPC分类号： H01L29/66575 , H01L21/265 , H01L21/28097 , H01L29/458 , H01L29/4908 , H01L29/4975 , H01L29/66507 , H01L29/66545 , H01L29/66772 , H01L29/78 , H01L29/7839
摘要： A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.
摘要翻译：场效应晶体管（FET）包括位于硅层中的源极/漏极硅化物区域; 位于源/漏硅化物区域和硅层之间的源极/漏极界面层; 以及包括位于硅层上的栅极氧化物层，位于栅极氧化物层上的栅极界面层和位于栅极界面层上的栅极硅化物的完全硅化栅极堆叠。

6. 发明授权

US08642407B2 Devices having reduced susceptibility to soft-error effects and method for fabrication 有权
标题翻译：降低了对软错误效应的敏感性的装置和制造方法
公开(公告)号：US08642407B2
公开(公告)日：2014-02-04
申请号：US12939506
申请日：2010-11-04
申请人： Tak H. Ning , Philip J. Oldiges
发明人： Tak H. Ning , Philip J. Oldiges
IPC分类号： H01L21/00
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878
摘要： A semiconductor-on-insulator (SOI) substrate complementary metal oxide semiconductor (CMOS) device and fabrication methods include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). Each of the PFET and the NFET include a transistor body of a first type of material and source and drain regions. The source and drain regions have a second type of material such that an injection charge into the source and drain region is greater than a parasitic charge into the transistor body to decrease parasitic bipolar current gain, increase critical charge (Qcrit) and reduce sensitivity to soft errors.
摘要翻译：绝缘体上半导体（SOI）衬底互补金属氧化物半导体（CMOS）器件和制造方法包括p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 PFET和NFET中的每一个包括第一类材料和源极和漏极区的晶体管体。源极和漏极区域具有第二类型的材料，使得源极和漏极区域中的注入电荷大于晶体管本体中的寄生电荷以降低寄生双极性电流增益，增加临界电荷（Qcrit）并降低对软件的灵敏度错误。

7. 发明授权

US08531001B2 Complementary bipolar inverter 有权
标题翻译：互补双极型逆变器
公开(公告)号：US08531001B2
公开(公告)日：2013-09-10
申请号：US13158419
申请日：2011-06-12
申请人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L21/70
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

8. 发明授权

US08415744B2 SOI CMOS circuits with substrate bias 有权
标题翻译： SOI CMOS电路具有衬底偏置
公开(公告)号：US08415744B2
公开(公告)日：2013-04-09
申请号：US13344006
申请日：2012-01-05
申请人： Jin Cai , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78648
摘要： The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.
摘要翻译：本发明涉及用于降低互补金属氧化物半导体（CMOS）中的n型场效应晶体管（n-FET）和p型场效应晶体管（p-FET）之间的阈值电压差的方法和装置）电路，其位于绝缘体上硅（SOI）衬底上。具体地，将衬底偏置电压施加到CMOS电路以差分调节n-FET和p-FET的阈值电压。例如，可以使用正的衬底偏置电压来降低n-FET的阈值电压，但是增加p-FET的阈值电压，而负的衬底偏置电压可以用于增加n-FET的阈值电压，但是减少p-FET的电流。此外，可以使用不同幅度和/或方向的两个或更多个衬底偏置电压来差分调节两个或更多个不同CMOS电路或CMOS电路组中的n-FET和p-FET阈值电压。

9. 发明授权

US08354858B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US08354858B2
公开(公告)日：2013-01-15
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

10. 发明授权

US08329564B2 Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method 有权
标题翻译：在SOI或体硅衬底上制造超陡逆行阱MOSFET的方法，以及根据该方法制造的器件
公开(公告)号：US08329564B2
公开(公告)日：2012-12-11
申请号：US11925069
申请日：2007-10-26
申请人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
发明人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
IPC分类号： H01L21/20
CPC分类号： H01L29/1083 , H01L21/28052 , H01L21/28088 , H01L21/28247 , H01L29/165 , H01L29/4933 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.
摘要翻译：提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。衬底可以是体积Si衬底或绝缘体上硅衬底。该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式