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    • 6. 发明授权
    • Trench isolation processes using polysilicon-assisted fill
    • 使用多晶硅辅助填料的沟槽隔离工艺
    • US06566228B1
    • 2003-05-20
    • US10083744
    • 2002-02-26
    • Jochen BeintnerRama DivakaruniJack A. MandelmanAndreas Knorr
    • Jochen BeintnerRama DivakaruniJack A. MandelmanAndreas Knorr
    • H01L2176
    • H01L21/76229H01L21/763H01L27/1052
    • Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.
    • 公开了一种同时提供用于由衬底材料制成的半导体衬底的阵列和支撑区域的沟槽隔离的方法,所述方法包括提供用于阵列和支撑区域的第一硬掩模层,所述第一硬掩模包括限定沟槽隔离的掩模开口 在阵列和支撑区域中,在阵列区域中提供深阵列沟槽隔离,在足以填充所述掩模开口和深阵列沟槽隔离的支撑和阵列区域上提供覆盖的平面化导电材料层,通过所述第一硬 掩模材料下降到所述半导体衬底中,以便形成支撑沟槽隔离,使得深阵列沟槽隔离和支撑沟槽隔离都具有相同的深度,并且其中包括一定数量的所述导电材料的导电元件保留在 每个所述深阵列沟槽。
    • 7. 发明申请
    • Method of making double-gated self-aligned finFET having gates of different lengths
    • 制造具有不同长度的栅极的双门控自对准finFET的方法
    • US20080176365A1
    • 2008-07-24
    • US12077973
    • 2008-03-24
    • Huilong ZhuBruce B. DorisXinlin WangJochen BeintnerYing ZhangPhilip J. Oldiges
    • Huilong ZhuBruce B. DorisXinlin WangJochen BeintnerYing ZhangPhilip J. Oldiges
    • H01L21/336
    • H01L29/785H01L29/66795H01L29/7855H01L29/7856
    • A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.
    • 提供了一种制造门控半导体器件的方法。 这种方法可以包括图案化衬底的单晶半导体区域,以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸,半导体 区域具有第一侧和第二侧,例如远离第一侧。 第一栅极可以形成在第一侧上,第一栅极在横向上具有第一栅极长度。 第二栅极可以形成在第二侧上,第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。 在一个实施例中,第二栅极长度可以比​​第一栅极长度短。 在一个实施例中,第一栅极可以主要由多晶硅锗组成,第二栅极可以由多晶硅组成。
    • 8. 发明授权
    • Structure and method of forming a notched gate field effect transistor
    • 形成陷波栅场效应晶体管的结构和方法
    • US07129564B2
    • 2006-10-31
    • US11059819
    • 2005-02-17
    • Jochen BeintnerYujun LiNaim MoumenPorshia Shane Wrschka
    • Jochen BeintnerYujun LiNaim MoumenPorshia Shane Wrschka
    • H01L31/117
    • H01L29/6659H01L21/26586H01L21/28044H01L21/28114H01L29/42376H01L29/49H01L29/665Y10S438/933
    • The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.
    • 本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。 栅电介质(例如栅极氧化物)形成在半导体衬底上的有源区的表面上,优选由隔离沟槽区限定。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗)(SiGe)。 然后横向蚀刻多晶硅层的侧壁,对SiGe层有选择性,以产生刻蚀的栅极导体结构,其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物,以降低栅极导体的电阻。 优选在完成晶体管时执行一个或多个其它处理步骤(例如源极和漏极注入,延伸注入和袖带轻掺杂漏极(LDD)注入),栅极导体堆叠掺杂和硅化。