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1. 发明授权

US08659054B2 Method and structure for pFET junction profile with SiGe channel 有权
标题翻译：具有SiGe通道的pFET结型材的方法和结构
公开(公告)号：US08659054B2
公开(公告)日：2014-02-25
申请号：US12905158
申请日：2010-10-15
申请人： Kern Rim , William K. Henson , Yue Liang , Xinlin Wang
发明人： Kern Rim , William K. Henson , Yue Liang , Xinlin Wang
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/425
CPC分类号： H01L29/1054 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/6659
摘要： A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.
摘要翻译：提供了包括位于硅锗（SiGe）沟道的表面上的p沟道场效应晶体管（pFET）器件的半导体结构，其中源极区和漏极区的结分布是突然的。在本公开内容中，通过在位于Si衬底之上的SiGe沟道层的正下方形成N或C掺杂的Si层来提供用于pFET器件的突发的源极/漏极结。因此，提供了其中N或C掺杂的Si层（夹在SiGe沟道层和Si衬底之间）对于p型掺杂剂具有与覆盖的SiGe沟道层大致相同的扩散速率的结构。由于N或C掺杂的Si层和上覆的SiGe沟道层对于p型掺杂物具有基本上相同的扩散率，并且因为N或C掺杂的Si层阻碍p型掺杂剂扩散到下面的Si 衬底，可以形成突发的源极/漏极结。

2. 发明申请

US20130320423A1 WRAP-AROUND FIN FOR CONTACTING A CAPACITOR STRAP OF A DRAM 有权
公开(公告)号：US20130320423A1
公开(公告)日：2013-12-05
申请号：US13484739
申请日：2012-05-31
申请人： Felix Beaudoin , Stephen M. Lucarini , Xinhui Wang , Xinlin Wang
发明人： Felix Beaudoin , Stephen M. Lucarini , Xinhui Wang , Xinlin Wang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10867 , H01L27/10826 , H01L27/10829 , H01L27/10879 , H01L27/1207 , H01L27/1211
摘要： A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

3. 发明授权

US07785944B2 Method of making double-gated self-aligned finFET having gates of different lengths 失效
标题翻译：制造具有不同长度的栅极的双门控自对准finFET的方法
公开(公告)号：US07785944B2
公开(公告)日：2010-08-31
申请号：US12077973
申请日：2008-03-24
申请人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
发明人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.
摘要翻译：提供了一种制造门控半导体器件的方法。这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体区域具有第一侧和第二侧，例如远离第一侧。第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。在一个实施例中，第二栅极长度可以比第一栅极长度短。在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

4. 发明授权

US07365378B2 MOSFET structure with ultra-low K spacer 失效
标题翻译： MOSFET结构采用超低K隔离
公开(公告)号：US07365378B2
公开(公告)日：2008-04-29
申请号：US11095373
申请日：2005-03-31
申请人： Elbert E. Huang , Philip J. Oldiges , Ghavam G. Shahidi , Christy S. Tyberg , Xinlin Wang , Robert L. Wisnieff
发明人： Elbert E. Huang , Philip J. Oldiges , Ghavam G. Shahidi , Christy S. Tyberg , Xinlin Wang , Robert L. Wisnieff
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/4991 , H01L29/4983 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.
摘要翻译： MOSFET结构和制造该结构的方法包括多层侧壁间隔物，以抑制栅极导体和源/漏扩展之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET性能。多层侧壁间隔物形成有介电常数等于1的间隙层和可渗透的低K（例如，小于3.5）的电介质层。或者，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二电介质层。多层间隔物也可以具有第三氮化物或氧化物隔离层。该第三间隔层提供增加的结构完整性。

5. 发明授权

US07348641B2 Structure and method of making double-gated self-aligned finFET having gates of different lengths 有权
标题翻译：制造具有不同长度的栅极的双门控自对准finFET的结构和方法
公开(公告)号：US07348641B2
公开(公告)日：2008-03-25
申请号：US10711182
申请日：2004-08-31
申请人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
发明人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A gated semiconductor device is provided, in which the body has a first dimension extending in a lateral direction parallel to a major surface of a substrate, and second dimension extending in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the body having a first side and a second side opposite the first side. The gated semiconductor device includes a first gate overlying the first side, and having a first gate length in the lateral direction. The gated semiconductor device further includes a second gate overlying the second side, the second gate having a second gate length in the lateral direction which is different from, and preferably shorter than the first gate length. In one embodiment, the first gate and the second gate being electrically isolated from each other. In another embodiment the first gate consists essentially of polycrystalline silicon germanium and the second gate consists essentially of polysilicon.
摘要翻译：提供了门控半导体器件，其中主体具有在平行于衬底的主表面的横向方向上延伸的第一尺寸，以及在至少基本上垂直且至少基本垂直于主表面的方向上延伸的第二尺寸，所述主体具有与所述第一侧相对的第一侧和第二侧。门控半导体器件包括覆盖第一侧的第一栅极，并且在横向上具有第一栅极长度。门控半导体器件还包括覆盖第二侧的第二栅极，第二栅极在横向上具有不同于第一栅极长度的第二栅极长度，并且优选地短于第一栅极长度。在一个实施例中，第一栅极和第二栅极彼此电隔离。在另一个实施例中，第一栅极主要由多晶硅锗组成，第二栅极主要由多晶硅组成。

6. 发明申请

US20050045947A1 THIN CHANNEL FET WITH RECESSED SOURCE/DRAINS AND EXTENSIONS 失效
标题翻译：具有残留源/漏极和扩展的薄沟道FET
公开(公告)号：US20050045947A1
公开(公告)日：2005-03-03
申请号：US10604907
申请日：2003-08-26
申请人： Huajie Chen , Bruce Doris , Philip Oldiges , Xinlin Wang , Huilong Zhu
发明人： Huajie Chen , Bruce Doris , Philip Oldiges , Xinlin Wang , Huilong Zhu
IPC分类号： H01L21/336 , H01L29/10 , H01L29/786 , H01L29/76 , H01L29/745 , H01L31/062
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/66772 , H01L29/78603 , H01L29/78618 , H01L29/78621 , H01L29/78684
摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin (smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer. Source/drain regions are located in recesses at either end of the thin channel and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain extensions and corresponding source/drain regions are self aligned to the FET gate and thin channel.
摘要翻译：包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。器件具有薄沟道，例如超薄（小于或等于10纳米（10nm））绝缘体上硅（SOI）层。源极/漏极区位于薄沟道的任一端的凹槽中，并且比薄沟道基本上更厚（例如，30nm）。源/漏扩展和相应的源极/漏极区域与FET栅极和薄沟道自对准。

7. 发明授权

US08466473B2 Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs 有权
标题翻译：具有高k /金属栅极MOSFET的Vt调谐和短沟道控制的结构和方法
公开(公告)号：US08466473B2
公开(公告)日：2013-06-18
申请号：US12960589
申请日：2010-12-06
申请人： Jin Cai , Xiangdong Chen , Xinlin Wang
发明人： Jin Cai , Xiangdong Chen , Xinlin Wang
IPC分类号： H01L31/0312 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L29/1041
摘要： A semiconductor device is provided that includes a semiconductor substrate having a well region located within an upper region thereof. A semiconductor material stack is located on the well region. The semiconductor material stack includes, from bottom to top, a semiconductor-containing buffer layer and a non-doped semiconductor-containing channel layer; the semiconductor-containing buffer layer of the semiconductor material stack is located directly on an upper surface of the well region. The structure also includes a gate material stack located directly on an upper surface of the non-doped semiconductor-containing channel layer. The gate material stack employed in the present disclosure includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a polysilicon layer.
摘要翻译：提供一种半导体器件，其包括具有位于其上部区域内的阱区的半导体衬底。半导体材料堆叠位于阱区上。半导体材料堆叠包括从底部到顶部的含半导体的缓冲层和非掺杂的含半导体的沟道层; 半导体材料堆叠的含半导体的缓冲层直接位于阱区的上表面。该结构还包括直接位于非掺杂半导体沟道层的上表面上的栅极材料堆叠。本公开中采用的栅极材料堆叠包括从底部到顶部的高k栅介质层，功函数金属层和多晶硅层。

8. 发明授权

US07692959B2 Multilayer storage class memory using externally heated phase change material 有权
标题翻译：使用外部加热相变材料的多层存储类存储器
公开(公告)号：US07692959B2
公开(公告)日：2010-04-06
申请号：US12107338
申请日：2008-04-22
申请人： Lia Krusin-Elbaum , Bruce G Elmegreen , Dennis M. Newns , Xinlin Wang
发明人： Lia Krusin-Elbaum , Bruce G Elmegreen , Dennis M. Newns , Xinlin Wang
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/71 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L27/2445 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity to the PCM element and configured to program the PCM element to one of a low resistance crystalline state and a high resistance amorphous state, and a second diode serving a sense diode for a current path used in reading the state of the PCM element; the base substrate further including decoding, programming and sensing circuitry formed therein, with each of the plurality of semiconductor layers spaced by an insulating layer; and intralayer wiring for communication between the base substrate circuitry and the array of memory cells in each of the semiconductor layers.
摘要翻译：多层相变材料（PCM）存储装置包括顺序地形成在基底基板上的多个半导体层，其中每个层包括形成在其中的存储单元的阵列，每个存储单元还包括PCM元件，第一二极管用作加热二极管，其热量接近PCM元件并且被配置为将PCM元件编程为低电阻晶体状态和高电阻非晶态之一，以及用于读取电流路径中的电流路径的感测二极管的第二二极管 PCM元素的状态; 所述基底基板还包括其中形成的解码，编程和感测电路，所述多个半导体层中的每一个由绝缘层隔开; 以及用于在基底基板电路和每个半导体层中的存储器单元阵列之间进行通信的层内布线。

9. 发明申请

US20090262572A1 MULTILAYER STORAGE CLASS MEMORY USING EXTERNALLY HEATED PHASE CHANGE MATERIAL 有权
标题翻译：使用外部加热相变材料的多层存储类存储器
公开(公告)号：US20090262572A1
公开(公告)日：2009-10-22
申请号：US12107338
申请日：2008-04-22
申请人： Lia KRUSIN-ELBAUM , Bruce G. ELMEGREEN , Dennis M. NEWNS , Xinlin WANG
发明人： Lia KRUSIN-ELBAUM , Bruce G. ELMEGREEN , Dennis M. NEWNS , Xinlin WANG
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/71 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L27/2445 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A multi-layer, phase change material (PCM) memory apparatus includes a plurality of semiconductor layers sequentially formed over a base substrate, wherein each layer comprises an array of memory cells formed therein, each memory cell further including a PCM element, a first diode serving as a heater diode in thermal proximity to the PCM element and configured to program the PCM element to one of a low resistance crystalline state and a high resistance amorphous state, and a second diode serving a sense diode for a current path used in reading the state of the PCM element; the base substrate further including decoding, programming and sensing circuitry formed therein, with each of the plurality of semiconductor layers spaced by an insulating layer; and intralayer wiring for communication between the base substrate circuitry and the array of memory cells in each of the semiconductor layers.
摘要翻译：多层相变材料（PCM）存储装置包括顺序地形成在基底基板上的多个半导体层，其中每个层包括形成在其中的存储单元的阵列，每个存储单元还包括PCM元件，第一二极管用作加热二极管，其热量接近PCM元件并且被配置为将PCM元件编程为低电阻晶体状态和高电阻非晶态之一，以及用于读取电流路径中的电流路径的感测二极管的第二二极管 PCM元素的状态; 所述基底基板还包括其中形成的解码，编程和感测电路，所述多个半导体层中的每一个由绝缘层隔开; 以及用于在基底基板电路和每个半导体层中的存储器单元阵列之间进行通信的层内布线。

10. 发明授权

US07385257B2 Hybrid orientation SOI substrates, and method for forming the same 有权
标题翻译：混合取向SOI衬底及其形成方法
公开(公告)号：US07385257B2
公开(公告)日：2008-06-10
申请号：US11411280
申请日：2006-04-26
申请人： Meikei Ieong , Xinlin Wang , Min Yang
发明人： Meikei Ieong , Xinlin Wang , Min Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.
摘要翻译：本发明涉及一种包含具有一个或多个第一器件区域的基底半导体衬底和位于基底半导体衬底之上的一个或多个第二器件区域的混合取向绝缘体上半导体（SOI）衬底结构。一个或多个第一器件区域包括具有位于顶部的第一半导体器件层的绝缘体层。一个或多个第二器件区域包括具有位于顶部的第二半导体器件层的反掺杂半导体层。第一和第二半导体器件层具有不同的晶体取向。优选地，第一（或第二）器件区域是n-FET器件区域，并且第一半导体器件层具有增强电子迁移率的晶体取向，而第二（或第一）器件区域是p-FET器件区域，并且第二半导体器件层具有增强空穴迁移率的不同的表面结晶取向。

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