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1. 发明授权

US06566228B1 Trench isolation processes using polysilicon-assisted fill 有权
标题翻译：使用多晶硅辅助填料的沟槽隔离工艺
公开(公告)号：US06566228B1
公开(公告)日：2003-05-20
申请号：US10083744
申请日：2002-02-26
申请人： Jochen Beintner , Rama Divakaruni , Jack A. Mandelman , Andreas Knorr
发明人： Jochen Beintner , Rama Divakaruni , Jack A. Mandelman , Andreas Knorr
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/763 , H01L27/1052
摘要： Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.
摘要翻译：公开了一种同时提供用于由衬底材料制成的半导体衬底的阵列和支撑区域的沟槽隔离的方法，所述方法包括提供用于阵列和支撑区域的第一硬掩模层，所述第一硬掩模包括限定沟槽隔离的掩模开口在阵列和支撑区域中，在阵列区域中提供深阵列沟槽隔离，在足以填充所述掩模开口和深阵列沟槽隔离的支撑和阵列区域上提供覆盖的平面化导电材料层，通过所述第一硬掩模材料下降到所述半导体衬底中，以便形成支撑沟槽隔离，使得深阵列沟槽隔离和支撑沟槽隔离都具有相同的深度，并且其中包括一定数量的所述导电材料的导电元件保留在每个所述深阵列沟槽。

2. 发明授权

US06348394B1 Method and device for array threshold voltage control by trapped charge in trench isolation 失效
标题翻译：用于沟槽隔离中捕获电荷的阵列阈值电压控制的方法和装置
公开(公告)号：US06348394B1
公开(公告)日：2002-02-19
申请号：US09573375
申请日：2000-05-18
申请人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
发明人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.
摘要翻译：提供半导体器件及其制造方法。在半导体衬底中形成沟槽。优选在沟槽的表面上形成薄的氧化物衬垫。氮化物衬垫形成在沟槽中。电荷被困在氮化物衬垫中。在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。优选地，氧化物填充物直接形成在氮化物衬垫上。

3. 发明授权

US06404000B1 Pedestal collar structure for higher charge retention time in trench-type DRAM cells 失效
标题翻译：基座领结构，在沟槽式DRAM单元中具有更高的电荷保留时间
公开(公告)号：US06404000B1
公开(公告)日：2002-06-11
申请号：US09599261
申请日：2000-06-22
申请人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
发明人： Rama Divakaruni , Rajarao Jammy , Byeong Y. Kim , Jack A. Mandelman , Akira Sudo , Dirk Tobben
IPC分类号： H01L2972
CPC分类号： H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.
摘要翻译：一种在衬底中形成有沟槽的存储器结构。环状氧化物位于沟槽的上部，并且包括基座部分。还公开了一种形成具有带衬垫环的环形氧化物的存储器件的方法。

4. 发明授权

US06288422B1 Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance 失效
标题翻译：用于制造具有垂直MOSFET和大沟槽电容的6F2 DRAM单元的结构和工艺
公开(公告)号：US06288422B1
公开(公告)日：2001-09-11
申请号：US09540276
申请日：2000-03-31
申请人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L27/10891 , H01L29/945
摘要： A 6F2 memory cell structure comprising a plurality of capacitors each located in a separate trench in a substrate; a pluralaity of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor being located above and electrically connected to a respective trench capacitor; a plurality of troughs in a striped pattern about said transistor, said troughs being spaced apart by a substantially uniform spacing, said plurality of striped troughs comprising a first group of troughs consisting of every other one of said troughs being filled with a dielectric material, and a second group of troughs being the remaining troughs of said plurality, said second group of troughs containing dielectric material, damascened wordlines and damascene wordline contacts; a respective wordline electrical contact connected to each respective gate conductor; and a bitline contacted to each bitline diffusion, wherein said bitline diffusions have a width defined by said spacing of said striped troughs and each wordline electrical contact is self-aligned to an edge of a trough of said second group of troughs.
摘要翻译： 6F2存储器单元结构，包括多个电容器，每个电容器位于衬底中的单独的沟槽中; 每个具有垂直栅极电介质，栅极导体和位线扩散的转移晶体管的多个，每个晶体管位于相应的沟槽电容器的上方并电连接到相应的沟槽电容器; 围绕所述晶体管的条纹图案的多个槽，所述槽以基本上均匀的间隔间隔开，所述多个条纹槽包括由每一个所述槽中的每一个填充有电介质材料构成的第一组槽，以及第二组槽是所述多个的剩余槽，所述第二组槽包含电介质材料，大阴影字线和大马士革字线触点; 连接到每个相应的栅极导体的相应字线电触头; 并且与每个位线扩散接触的位线，其中所述位线扩散具有由所述条纹槽的所述间隔限定的宽度，并且每个字线电触点与所述第二组槽的槽的边缘自对准。

5. 发明授权

US06759291B2 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06759291B2
公开(公告)日：2004-07-06
申请号：US10045499
申请日：2002-01-14
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

6. 发明授权

US06369419B1 Self-aligned near surface strap for high density trench DRAMS 失效
标题翻译：用于高密度沟槽DRAMS的自对准近表面带
公开(公告)号：US06369419B1
公开(公告)日：2002-04-09
申请号：US09603657
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
发明人： Ramachandra Divakaruni , Jochen Beintner , Jack A. Mandelman , Ulrike Gruening , Johann Alsmeier , Gary Bronner
IPC分类号： H01L2994
CPC分类号： H01L27/10867
摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.
摘要翻译：一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形形结构。此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

7. 发明授权

US06204140B1 Dynamic random access memory 有权
标题翻译：动态随机存取存储器
公开(公告)号：US06204140B1
公开(公告)日：2001-03-20
申请号：US09275337
申请日：1999-03-24
申请人： Ulrike Gruening , Jochen Beintner , Scott Halle , Jack A. Mandelman , Carl J. Radens , Juergen Wittmann , Jeffrey J. Welser
发明人： Ulrike Gruening , Jochen Beintner , Scott Halle , Jack A. Mandelman , Carl J. Radens , Juergen Wittmann , Jeffrey J. Welser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10861
摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.
摘要翻译：一种方法包括在半导体本体中形成沟槽电容器。在电容器的上部形成凹部，该凹槽在半导体本体中具有侧壁。第一材料沉积在凹槽的侧壁和底部上方。第二种材料沉积在第一种材料上。在第二材料上提供面罩。掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹部底部的另一部分以暴露第二材料的下面部分。第二材料的暴露的下部部分的部分是选择性地去除，同时留下基本未蚀刻的暴露的第一材料的下部。选择性地去除半导体主体的第一材料和下部的暴露部分。隔离区形成在半导体本体的去除部分中。所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分，第二材料的部分。在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。通过这种方法，允许更大的掩模不对准公差。

8. 发明授权

US06762447B1 Field-shield-trench isolation for gigabit DRAMs 有权
标题翻译：用于千兆位DRAM的场屏蔽沟槽隔离
公开(公告)号：US06762447B1
公开(公告)日：2004-07-13
申请号：US09245269
申请日：1999-02-05
申请人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/763 , H01L21/765 , H01L27/10829 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.
摘要翻译：形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于与半导体本体电接触。隔离沟槽的上部填充有第二电绝缘体。

9. 发明授权

US06897107B2 Method for forming TTO nitride liner for improved collar protection and TTO reliability 失效
标题翻译：用于形成TTO氮化物衬垫以改善套环保护和TTO可靠性的方法
公开(公告)号：US06897107B2
公开(公告)日：2005-05-24
申请号：US10720490
申请日：2003-11-24
申请人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachajam C. Jaiprakash
发明人： Rama Divakaruni , Thomas W. Dyer , Rajeev Malik , Jack A. Mandelman , Venkatachajam C. Jaiprakash
IPC分类号： H01L21/316 , H01L21/318 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.
摘要翻译：在垂直MOSFET DRAM单元器件形成期间，能够在沟槽顶氧化物TTO（高密度等离子体）HDP沉积之前沉积薄氮化物衬垫的结构和方法。随后在TTO侧壁蚀刻之后移除该衬垫。该衬垫的一个功能是在TTO氧化物侧壁蚀刻期间保护套环氧化物不被蚀刻，并且通常提供在当前处理方案中未实现的横向蚀刻保护。工艺顺序不依赖于以前沉积的膜用于套环保护，并且将TTO侧壁蚀刻保护与先前的处理步骤解耦以提供附加的工艺灵活性，例如在节点氮化物去除期间允许更薄的带切割掩模氮化物和更大的氮化物蚀刻和掩埋带氮化界面去除。有利地，在TTO之下的氮化物衬垫的存在降低了垂直MOSFET DRAM单元的栅极和电容器节点电极之间的TTO介质击穿的可能性，同时确保带扩散到栅极导体重叠。

10. 发明授权

US06501131B1 Transistors having independently adjustable parameters 有权
标题翻译：晶体管具有可独立调节的参数
公开(公告)号：US06501131B1
公开(公告)日：2002-12-31
申请号：US09359291
申请日：1999-07-22
申请人： Rama Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
发明人： Rama Divakaruni , Jeffrey P. Gambino , Jack A. Mandelman , Rajesh Rengarajan
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823807 , H01L29/66492 , H01L29/66537 , H01L29/66583
摘要： The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.
摘要翻译：制造半导体器件如MOSFET的工艺规则被修改，以提供遵循常规栅极侧壁氧化步骤的双重功能掺杂，大大降低了热预算和硼渗透问题。通过允许减小的间隙宽高比同时保持低的薄层电阻值的装置结构，热预算的关注进一步显着降低。减小的间隙宽高比也放松了对高回流电介质材料的需要，并且还有助于使用倾斜的源漏（S-D）和晕轮植入物。还提供了用于产生MOSFET沟道，横向掺杂分布的新型结构和工艺，其抑制短沟道效应，同时提供低S-D结电容和泄漏，以及对热载流子效应的抗扰性。这也提供了减小接触柱对栅极导体电容的可能性，因为可以用氧化物栅极侧壁间隔物形成无边界接触。结果，S-D结可以独立于栅极导体掺杂掺杂，更容易地允许各种MOSFET结构。

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