专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06566696B1 Self-aligned VT implant 有权
标题翻译：自对准VT植入
公开(公告)号：US06566696B1
公开(公告)日：2003-05-20
申请号：US09907359
申请日：2001-07-17
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L2980
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供了具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

2. 发明授权

US06506642B1 Removable spacer technique 有权
标题翻译：可拆卸间隔技术
公开(公告)号：US06506642B1
公开(公告)日：2003-01-14
申请号：US10020931
申请日：2001-12-19
申请人： Scott D. Luning , Jon D. Cheek , Daniel Kadosh , James F. Buller , David E. Brown
发明人： Scott D. Luning , Jon D. Cheek , Daniel Kadosh , James F. Buller , David E. Brown
IPC分类号： H01L218238
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6656
摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.
摘要翻译：亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物，在栅电极的已经被去除了第一侧壁间隔物的侧表面上。实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。

3. 发明授权

US06720227B1 Method of forming source/drain regions in a semiconductor device 失效
标题翻译：在半导体器件中形成源/漏区的方法
公开(公告)号：US06720227B1
公开(公告)日：2004-04-13
申请号：US10059615
申请日：2002-01-29
申请人： Daniel Kadosh , Jon D. Cheek , James F. Buller , Basab Bandyopadhyay
发明人： Daniel Kadosh , Jon D. Cheek , James F. Buller , Basab Bandyopadhyay
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/7833
摘要： A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.
摘要翻译：提供了一种在半导体器件中形成源极/漏极区域的方法。在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，通过至少执行以下步骤在衬底中邻近栅电极形成源极/漏极区：执行两个离子注入工艺以形成用于并且执行第三离子注入工艺以进一步形成用于该器件的源极/漏极区域。本发明可以使用各种N型和P型掺杂剂原子，例如砷，磷，硼和二氟化硼。

4. 发明授权

US06274415B1 Self-aligned Vt implant 有权
标题翻译：自对准Vt植入物
公开(公告)号：US06274415B1
公开(公告)日：2001-08-14
申请号：US09489068
申请日：2000-01-21
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L21337
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

5. 发明授权

US06245649B1 Method for forming a retrograde impurity profile 有权
标题翻译：形成逆行杂质分布的方法
公开(公告)号：US06245649B1
公开(公告)日：2001-06-12
申请号：US09251923
申请日：1999-02-17
申请人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
发明人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L2104
CPC分类号： H01L29/105 , H01L21/2652
摘要： A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.
摘要翻译：提供了一种在半导体衬底中形成逆向杂质分布的方法。该方法包括在半导体衬底的表面上形成具有在大约至大约的范围内的厚度的牺牲层。此后，进行离子注入工艺，其中掺杂杂质离子在有效地在半导体衬底中形成逆向杂质分布的条件下引导通过牺牲层并进入半导体衬底。

6. 发明授权

US06541321B1 Method of making transistors with gate insulation layers of differing thickness 有权
标题翻译：制造具有不同厚度的栅极绝缘层的晶体管的方法
公开(公告)号：US06541321B1
公开(公告)日：2003-04-01
申请号：US10145519
申请日：2002-05-14
申请人： James F. Buller , Jon D. Cheek
发明人： James F. Buller , Jon D. Cheek
IPC分类号： H01L21336
CPC分类号： H01L21/823462
摘要： In one illustrative embodiment, the method comprises forming a sacrificial layer of material above a substrate comprised of silicon, performing a wet etching process to remove the sacrificial layer, implanting fluorine atoms into selected portions of the substrate after the sacrificial layer is removed, and performing a thermal oxidation process to form a plurality of gate insulation layers above the substrate, the gate insulation layers formed above the fluorine implanted selected portions of the substrate having a thickness that is greater than a thickness of the gate insulation layers formed above portions of the substrate not implanted with fluorine.
摘要翻译：在一个说明性实施例中，该方法包括在由硅构成的衬底之上形成材料的牺牲层，执行湿蚀刻工艺以去除牺牲层，在去除牺牲层之后将氟原子注入到衬底的选定部分中，并执行热氧化工艺以在衬底上形成多个栅极绝缘层，形成在衬底的氟注入的选定部分上方的栅极绝缘层的厚度大于在衬底的上方形成的栅极绝缘层的厚度没有植入氟。

7. 发明授权

US07179745B1 Method for offsetting a silicide process from a gate electrode of a semiconductor device 失效
标题翻译：将硅化物工艺与半导体器件的栅电极相抵消的方法
公开(公告)号：US07179745B1
公开(公告)日：2007-02-20
申请号：US10860100
申请日：2004-06-04
申请人： Andrew M. Waite , Jon D. Cheek , David Brown
发明人： Andrew M. Waite , Jon D. Cheek , David Brown
IPC分类号： H01L21/311
CPC分类号： H01L29/7843 , H01L29/665 , H01L29/6653 , H01L29/66772
摘要： A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.
摘要翻译：一种用于在具有多晶硅栅电极，衬底中的源极和漏极区域以及衬底中的源极和漏极延伸部分的半导体器件上偏移硅化物的方法，在多晶硅栅电极的侧壁上采用氮化钛侧壁间隔物。氮化钛侧壁间隔物防止了在氧化过程中在源极和漏极延伸部分顶部的硅化物生长。然后通过蚀刻工艺去除氮化钛侧壁间隔物，该蚀刻工艺不蚀刻在源极和漏极区域以及多晶硅栅极电极中形成的硅化物区域。在移除氮化钛侧壁间隔物之后，可以将低k层间介电层或应力衬垫沉积在器件的顶部以增强器件性能。

8. 发明授权

US06426262B1 Method of analyzing the effects of shadowing of angled halo implants 失效
标题翻译：分析角度晕轮植入物阴影效应的方法
公开(公告)号：US06426262B1
公开(公告)日：2002-07-30
申请号：US09644735
申请日：2000-08-23
申请人： Mark Brandon Fuselier , Jon D. Cheek , Frederick N. Hause , Marilyn I. Wright
发明人： Mark Brandon Fuselier , Jon D. Cheek , Frederick N. Hause , Marilyn I. Wright
IPC分类号： H01L218236
CPC分类号： H01L29/66492 , H01L21/26586
摘要： The present invention is directed to a method that comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.
摘要翻译：本发明涉及一种包括形成多个晶体管的方法，每个晶体管具有至少一个栅电极，并且在晶体管中形成晕圈注入区，同时改变光晕注入角，掩模层高度和屏蔽层与晶体管的栅电极的横向偏移。该方法还包括确定晶体管中的至少一些晶体管的电性能特征，其中，所述卤素注入角，掩模层高度和掩模层的横向偏移中的至少一个不同，以及将所确定的电性能特性晶体管。

9. 发明授权

US06406964B1 Method of controlling junction recesses in a semiconductor device 有权
标题翻译：控制半导体器件中的接合凹部的方法
公开(公告)号：US06406964B1
公开(公告)日：2002-06-18
申请号：US09704008
申请日：2000-11-01
申请人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
发明人： Derick J. Wristers , Jon D. Cheek , John G. Pellerin
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/665 , H01L29/7833
摘要： The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implant process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.
摘要翻译：本发明涉及一种形成晶体管的方法。在一个实施例中，所述方法包括提供衬底，所述衬底被掺杂有第一类型的掺杂剂材料，在由所述隔离结构限定的所述衬底的有源区域中的所述衬底上形成晶体管，以及执行至少一个离子注入在与晶体管的栅电极相邻的衬底中注入掺杂剂原子的工艺。该方法还包括在晶体管上执行与第一类掺杂剂材料相反类型的掺杂剂材料的至少两个成角度的离子注入工艺，并执行至少一个退火工艺。

10. 发明授权

US06316302B1 Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant 有权
标题翻译：各向同性蚀刻要用于NMOS源极/漏极注入和PMOS LDD植入物的侧壁间隔物
公开(公告)号：US06316302B1
公开(公告)日：2001-11-13
申请号：US09604051
申请日：2000-06-26
申请人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
发明人： Jon D. Cheek , Derick J. Wristers , Anthony J. Toprac
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/823864 , H01L29/6656
摘要： A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
摘要翻译：提供了一种用于各向同性蚀刻侧壁间隔物对以减少每个侧壁间隔物的横向厚度的方法。在一个实施例中，第一和第二对侧壁间隔件同时形成在相应的第一和第二栅极导体的相对的侧壁表面上。第一和第二栅极导体分别在半导体衬底的隔离的第一和第二有源区域上横向间隔开。有利地，在形成PMOS晶体管的NMOS晶体管和LDD区域的源极和漏极区域期间，单个侧壁间隔物对被用作掩模结构。也就是说，在减少侧壁间隔物的横向厚度之前，n +源极/漏极（“S / D”）植入物在第一对侧壁间隔物的外侧边缘上自对准。然而，在间隔物厚度减小之后，p-LDD植入物自对准到第二对侧壁间隔物的外侧边缘。因此，不需要在栅极导体的侧壁表面附近形成多对侧壁间隔件，以改变注入区域和后续集成电路的栅极导体之间的间隔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式