专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06506642B1 Removable spacer technique 有权
标题翻译：可拆卸间隔技术
公开(公告)号：US06506642B1
公开(公告)日：2003-01-14
申请号：US10020931
申请日：2001-12-19
申请人： Scott D. Luning , Jon D. Cheek , Daniel Kadosh , James F. Buller , David E. Brown
发明人： Scott D. Luning , Jon D. Cheek , Daniel Kadosh , James F. Buller , David E. Brown
IPC分类号： H01L218238
CPC分类号： H01L29/6653 , H01L21/823814 , H01L21/823864 , H01L29/6656
摘要： Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.
摘要翻译：亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物，在栅电极的已经被去除了第一侧壁间隔物的侧表面上。实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。

2. 发明授权

US06787464B1 Method of forming silicide layers over a plurality of semiconductor devices 失效
标题翻译：在多个半导体器件上形成硅化物层的方法
公开(公告)号：US06787464B1
公开(公告)日：2004-09-07
申请号：US10189048
申请日：2002-07-02
申请人： Jon D. Cheek , Scott D. Luning
发明人： Jon D. Cheek , Scott D. Luning
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/823418 , H01L21/823443 , H01L21/823456 , H01L21/823814 , H01L21/823835 , H01L21/82385 , H01L29/7833
摘要： The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of at least a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors. In yet another illustrative embodiment, the method comprises forming a layer of refractory metal to an original thickness above a plurality of transistors, reducing the original thickness of a portion of the layer of refractory metal above at least some of the transistors to define a layer of refractory metal having multiple thicknesses, and performing at least one anneal process to convert portions of the layer of refractory metal having multiple thicknesses to metal silicide regions on the transistors.
摘要翻译：本发明一般涉及基于栅极临界尺寸在晶体管上形成金属硅化物区域的各种方法。在一个说明性实施例中，该方法包括在多个晶体管上形成难熔金属层，减少至少部分晶体管的至少一部分难熔金属的厚度，并执行至少一个退火工艺以形成晶体管上方的金属硅化物区域。在另一示例性实施例中，该方法包括在多个晶体管上方形成难熔金属层，减小了具有栅极电极的第一晶体管之上的难熔金属层的厚度，临界尺寸小于临界尺寸的多个晶体管中的另一个晶体管的栅极电极结构，并且执行至少一个退火工艺以在所述多个晶体管上形成金属硅化物区域。在另一个说明性实施例中，该方法包括在多个晶体管上方形成原始厚度的难熔金属层，将难熔金属层的一部分的一部分的原始厚度减小到至少一些晶体管之上以限定一层具有多个厚度的难熔金属，并且执行至少一个退火工艺以将具有多个厚度的难熔金属层的部分转换成晶体管上的金属硅化物区域。

3. 发明授权

US06372587B1 Angled halo implant tailoring using implant mask 有权
标题翻译：使用植入物掩模的角度光晕植入物定制
公开(公告)号：US06372587B1
公开(公告)日：2002-04-16
申请号：US09568069
申请日：2000-05-10
申请人： Jon D. Cheek , Scott D. Luning , Derick J. Wristers
发明人： Jon D. Cheek , Scott D. Luning , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness &tgr; above the surface and having an edge disposed a distance &dgr; from the first edge of the structure. The method also includes implanting the halo implant at an angle &agr; with respect to a direction perpendicular to the surface, wherein the tangent of the angle &agr; is at least the ratio of the distance &dgr; to the thickness &tgr;.
摘要翻译：提供了一种用于在邻近结构的一侧的衬底中形成卤素注入的方法，所述方法包括在所述衬底的表面上方形成所述结构，所述结构具有第一和第二边缘并且形成限定邻近所述结构的区域的掩模，该面具具有厚度＆tgr; 并且具有与结构的第一边缘相距一定距离的边缘。该方法还包括将晕圈植入物相对于垂直于该表面的方向以角度α注入，其中角度α的切线至少为距离δ与厚度的比值。

4. 发明授权

US06589847B1 Tilted counter-doped implant to sharpen halo profile 有权
标题翻译：倾斜反掺杂植入物以锐化晕轮廓
公开(公告)号：US06589847B1
公开(公告)日：2003-07-08
申请号：US09631557
申请日：2000-08-03
申请人： Daniel Kadosh , Scott D. Luning , Derick J. Wristers
发明人： Daniel Kadosh , Scott D. Luning , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/1045 , H01L29/6656
摘要： The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and forming halo implant regions in the substrate adjacent the gate electrode by performing at least the following steps: performing a first angled implant process using a dopant material that is of a type opposite to the first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material. The method concludes with performing at least one additional implantation process to further form source/drain regions for the device.
摘要翻译：本发明涉及一种在半导体器件中形成卤素注入区的方法。在一个说明性实施例中，该方法包括在半导体衬底之上形成栅电极，该衬底被掺杂有第一种类型的掺杂剂材料，以及通过至少执行以下步骤在邻近栅极的衬底中形成卤素注入区域：执行使用与第一类型的掺杂剂材料相反的类型的掺杂剂材料并使用与第一类型的掺杂剂材料具有相同类型的掺杂剂材料来执行第二成角度的注入的第一成角度注入工艺。该方法的结论是执行至少一个额外的注入工艺以进一步形成器件的源极/漏极区域。

5. 发明授权

US06777281B1 Maintaining LDD series resistance of MOS transistors by retarding dopant segregation 失效
标题翻译：通过延迟掺杂剂分离来维持MOS晶体管的LDD串联电阻
公开(公告)号：US06777281B1
公开(公告)日：2004-08-17
申请号：US10214361
申请日：2002-08-08
申请人： Daniel Kadosh , Scott D. Luning , Akif Sultan , David Wu
发明人： Daniel Kadosh , Scott D. Luning , Akif Sultan , David Wu
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/3115 , H01L21/31155 , H01L21/823814 , H01L29/6656
摘要： A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semi conductor substrate including at least one dopant species-containing region extending to a surface of the substrate; (b) forming a thin liner oxide layer on the surface of the substrate; and (c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：（a）提供半导体衬底，其包括至少一个延伸到衬底表面的含掺杂物种的区域;（b）在衬底的表面上形成薄的衬里氧化物层基材; 和（c）在细线氧化物层中并入至少一种物质，其至少一种物质，其基本上防止或至少减少其中从至少一种含掺杂物种的区域移动而引起的掺杂物质的偏析。

6. 发明申请

US20090236664A1 INTEGRATION SCHEME FOR CONSTRAINED SEG GROWTH ON POLY DURING RAISED S/D PROCESSING 审中-公开
标题翻译：在加速S / D处理期间聚合的SEG增长的集成方案
公开(公告)号：US20090236664A1
公开(公告)日：2009-09-24
申请号：US12471600
申请日：2009-05-26
申请人： David E. Brown , Scott D. Luning
发明人： David E. Brown , Scott D. Luning
IPC分类号： H01L29/786
CPC分类号： H01L29/66545 , H01L21/0206 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.
摘要翻译：提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。该方法适用于集成到集成电路半导体器件的制造工艺中。该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。

7. 发明授权

US07553732B1 Integration scheme for constrained SEG growth on poly during raised S/D processing 有权
标题翻译：在提升的S / D处理期间，聚合物对SEG增长的集成方案
公开(公告)号：US07553732B1
公开(公告)日：2009-06-30
申请号：US11150923
申请日：2005-06-13
申请人： David E. Brown , Scott D. Luning
发明人： David E. Brown , Scott D. Luning
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/0206 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.
摘要翻译：提出了一种限制在外延硅生长过程中形成的栅极盖的横向生长以在多晶硅上实现凸起的源极/漏极区域的方法。该方法适用于集成到集成电路半导体器件的制造工艺中。该方法利用选择性蚀刻工艺，取决于包含栅极上的保护层（硬掩模）的材料和间隔物的材料，例如氧化物掩模/氮化物间隔物或氮化物掩模/氧化物间隔物。

8. 发明授权

US07910996B2 Semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07910996B2
公开(公告)日：2011-03-22
申请号：US12496133
申请日：2009-07-01
申请人： Paul R. Besser , Scott D. Luning
发明人： Paul R. Besser , Scott D. Luning
IPC分类号： H01L29/12
CPC分类号： H01L29/66628 , H01L29/66772
摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.
摘要翻译：公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。隔离材料凹陷在半导体层的主表面下方的沟槽区域内。形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

9. 发明授权

US06743685B1 Semiconductor device and method for lowering miller capacitance for high-speed microprocessors 失效
标题翻译：用于降低高速微处理器的磨机电容的半导体器件和方法
公开(公告)号：US06743685B1
公开(公告)日：2004-06-01
申请号：US09784629
申请日：2001-02-15
申请人： David D. Wu , Michael P. Duane , Scott D. Luning
发明人： David D. Wu , Michael P. Duane , Scott D. Luning
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/26586 , H01L21/28202 , H01L29/4983 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66492 , H01L29/7833
摘要： A method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the cage region of the doped-poly gate structure adjacent the gate dielectric.
摘要翻译：提供了一种方法，所述方法包括在衬底的表面上形成栅极电介质，并在栅极电介质上方形成掺杂多晶硅栅极结构，所述掺杂 - 多晶硅结构具有边缘区域。该方法还包括在与栅极电介质相邻的掺杂多晶硅栅极结构的笼状区域中形成掺杂剂贫化多晶硅区域。

10. 发明授权

US6025240A Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 失效
公开(公告)号：US6025240A
公开(公告)日：2000-02-15
申请号：US993600
申请日：1997-12-18
申请人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
发明人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式