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1. 发明授权

US06274415B1 Self-aligned Vt implant 有权
标题翻译：自对准Vt植入物
公开(公告)号：US06274415B1
公开(公告)日：2001-08-14
申请号：US09489068
申请日：2000-01-21
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L21337
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

2. 发明授权

US06566696B1 Self-aligned VT implant 有权
标题翻译：自对准VT植入
公开(公告)号：US06566696B1
公开(公告)日：2003-05-20
申请号：US09907359
申请日：2001-07-17
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L2980
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供了具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

3. 发明授权

US06245649B1 Method for forming a retrograde impurity profile 有权
标题翻译：形成逆行杂质分布的方法
公开(公告)号：US06245649B1
公开(公告)日：2001-06-12
申请号：US09251923
申请日：1999-02-17
申请人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
发明人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L2104
CPC分类号： H01L29/105 , H01L21/2652
摘要： A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.
摘要翻译：提供了一种在半导体衬底中形成逆向杂质分布的方法。该方法包括在半导体衬底的表面上形成具有在大约至大约的范围内的厚度的牺牲层。此后，进行离子注入工艺，其中掺杂杂质离子在有效地在半导体衬底中形成逆向杂质分布的条件下引导通过牺牲层并进入半导体衬底。

4. 发明授权

US07417250B1 Strained-silicon device with different silicon thicknesses 有权
标题翻译：具有不同硅厚度的应变硅器件
公开(公告)号：US07417250B1
公开(公告)日：2008-08-26
申请号：US11151550
申请日：2005-06-14
申请人： James F. Buller , Derick J Wristers , Qi Xiang , Bin Yu
发明人： James F. Buller , Derick J Wristers , Qi Xiang , Bin Yu
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L29/1054
摘要： A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。最初，应变硅层的第一和第二部分最初可以具有相同的厚度。在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。还公开了一种半导体器件。

5. 发明授权

US06936506B1 Strained-silicon devices with different silicon thicknesses 有权
标题翻译：具有不同硅厚度的应变硅器件
公开(公告)号：US06936506B1
公开(公告)日：2005-08-30
申请号：US10442975
申请日：2003-05-22
申请人： James F. Buller , Derick J. Wristers , Qi Xiang , Bin Yu
发明人： James F. Buller , Derick J. Wristers , Qi Xiang , Bin Yu
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/10
CPC分类号： H01L21/823807 , H01L29/1054
摘要： A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。最初，应变硅层的第一和第二部分最初可以具有相同的厚度。在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。还公开了一种半导体器件。

6. 发明授权

US06727534B1 Electrically programmed MOS transistor source/drain series resistance 有权
标题翻译：电子编程MOS晶体管源极/漏极串联电阻
公开(公告)号：US06727534B1
公开(公告)日：2004-04-27
申请号：US10022847
申请日：2001-12-20
申请人： James F. Buller , Qi Xiang , Derick J. Wristers
发明人： James F. Buller , Qi Xiang , Derick J. Wristers
IPC分类号： H01L2979
CPC分类号： H01L29/4983 , H01L29/42376 , H01L29/66484 , H01L29/6656
摘要： High-speed MOS transistors are provided by forming a conductive layer embedded in transistor gate sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode and the source/drain regions of the transistor. The embedded conductive layer is positioned over the source/drain extensions and causes charge to accumulate in the source/drain extensions lowering the series resistance of the source/drain regions.
摘要翻译：通过形成嵌入在晶体管栅极侧壁间隔物中的导电层来提供高速MOS晶体管。嵌入式导电层与晶体管的栅极电极和源极/漏极区域电绝缘。嵌入的导电层位于源极/漏极延伸部分上方，并使电荷累积在源极/漏极延伸部中，从而降低源极/漏极区域的串联电阻。

7. 发明授权

US06727136B1 Formation of ultra-shallow depth source/drain extensions for MOS transistors 有权
标题翻译：形成MOS晶体管的超浅深度源极/漏极延伸
公开(公告)号：US06727136B1
公开(公告)日：2004-04-27
申请号：US10273291
申请日：2002-10-18
申请人： James F. Buller , Derick J. Wristers , David Wu , Akif Sultan
发明人： James F. Buller , Derick J. Wristers , David Wu , Akif Sultan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/823418 , H01L21/823814 , H01L29/1054 , H01L29/7833
摘要： A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semiconductor material; and (b) introducing a dopant-containing species of one conductivity type into at least one pre-selected portion of the strained lattice layer of first semiconductor material to form a dopant-containing region therein with a junction at a depth substantially equal to the pre-selected thickness, wherein the second semiconductor material of the underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.
摘要翻译：一种制造半导体器件的方法，包括以下顺序的步骤：（a）提供半导体衬底，该半导体衬底在其上表面包括预先选定的第一半导体材料的应变晶格层和第二半导体材料的下层; 和（b）将含有一种导电类型的含掺杂剂的物质引入到第一半导体材料的应变晶格层的至少一个预先选择的部分中，以在其中形成含有掺杂剂的区域，其中接合部的深度基本上等于预先 - 选择的厚度，其中下层的第二半导体材料抑制来自应变晶格层的含掺杂剂物质的扩散，从而将结的深度控制/限制到基本上预应变晶格层的预选厚度。

8. 发明授权

US06707106B1 Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer 有权
标题翻译：具有由埋置氧化物层中的压缩材料引入的拉伸应变硅的半导体器件
公开(公告)号：US06707106B1
公开(公告)日：2004-03-16
申请号：US10272979
申请日：2002-10-18
申请人： Derick J. Wristers , Qi Xiang , James F. Buller
发明人： Derick J. Wristers , Qi Xiang , James F. Buller
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/66772 , H01L29/7846 , H01L29/78603
摘要： A semiconductor device is provided with the high-speed capabilities of silicon on insulator (SOI) and strained silicon technologies, without requiring the formation of a silicon germanium layer. A layer of compressive material is formed on a SOI semiconductor substrate to induce strain in the overlying silicon layer. The compressive materials include silicon oxynitride, phosphorous, silicon nitride, and boron/phosphorous doped silica glass.
摘要翻译：半导体器件具有绝缘体上硅（SOI）和应变硅技术的高速能力，而不需要形成硅锗层。在SOI半导体衬底上形成一层压缩材料，以在上层硅层中引起应变。压缩材料包括氮氧化硅，磷，氮化硅和掺杂硼/磷的二氧化硅玻璃。

9. 发明授权

US5976925A Process of fabricating a semiconductor devise having asymmetrically-doped active region and gate electrode 失效
标题翻译：制造具有非对称掺杂有源区和栅电极的半导体器件的工艺
公开(公告)号：US5976925A
公开(公告)日：1999-11-02
申请号：US980636
申请日：1997-12-01
申请人： Jon Cheek , Derick J. Wristers , James F. Buller
发明人： Jon Cheek , Derick J. Wristers , James F. Buller
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/6659 , H01L21/823418 , H01L29/665
摘要： A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a first dopant to form a doped polysilicon layer. Portions of the doped polysilicon layer are then removed to form at least one gate electrode. Active regions of the substrate adjacent the gate electrode are implanted with a second dopant to form source/drain regions in the substrate. In this manner, the implant used to form the source/drain regions may be decoupled from the implant used to form the gate electrode. This, for example, allows for shallower source/drain regions to be formed without the formation of the depletion layer in the gate electrode.
摘要翻译：提供具有非对称掺杂的栅电极和有源区的半导体器件和制造这种器件的工艺。根据本发明的一个实施例，在衬底上形成多晶硅层。然后用第一掺杂剂注入多晶硅层以形成掺杂多晶硅层。然后去除掺杂多晶硅层的部分以形成至少一个栅电极。与栅电极相邻的衬底的有源区注入第二掺杂剂以在衬底中形成源极/漏极区。以这种方式，用于形成源极/漏极区域的植入物可以与用于形成栅电极的植入物去耦合。例如，这允许形成更浅的源/漏区，而不在栅电极中形成耗尽层。

10. 发明授权

US06801096B1 Ring oscillator with embedded scatterometry grate array 有权
标题翻译：环形振荡器带有嵌入式散射仪格栅阵列
公开(公告)号：US06801096B1
公开(公告)日：2004-10-05
申请号：US10348014
申请日：2003-01-22
申请人： Hormuzdiar E. Nariman , Derick J. Wristers , James F. Buller
发明人： Hormuzdiar E. Nariman , Derick J. Wristers , James F. Buller
IPC分类号： H03B2700
CPC分类号： H01L27/088 , H03K3/0315
摘要： A MOS ring oscillator includes a number of serially connected inverter stages with each stage comprising a MOS transistor pair. At least one of the transistors also comprises a scatterometry grate array, which is used during manufacturing of the ring oscillator to obtain scatterometry measurements that allow polysilicon lines of the MOS ring oscillator to have widths of less than 60 nm. A method includes forming at least one grate array above a substrate, illuminating the grate array, measuring light reflected off of the grate array to generate an optical characteristic trace for the grate array, and comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a grate array having a desired profile. The generated trace can further be used to calibrate the ring oscillator
摘要翻译： MOS环形振荡器包括多个串联的反相器级，每级包括一个MOS晶体管对。至少一个晶体管还包括散射测量格栅阵列，其在环形振荡器的制造期间使用以获得允许MOS环形振荡器的多晶硅线具有小于60nm的宽度的散射测量。一种方法包括在衬底上形成至少一个格栅阵列，照亮格栅阵列，测量从格栅阵列反射的光，以产生格栅阵列的光学特征曲线，并将生成的光学特征曲线与目标光学特征曲线对应于具有所需轮廓的炉排阵列。产生的轨迹可进一步用于校准环形振荡器

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