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1. 发明授权

US08461016B2 Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation 有权
标题翻译：集成电路器件和形成存储器阵列和外围电路隔离的方法
公开(公告)号：US08461016B2
公开(公告)日：2013-06-11
申请号：US13268066
申请日：2011-10-07
申请人： James Mathew , Brett D. Lowe , Yunjun Ho , H. Jim Fulford , Jie Sun , Zhaoli Sun
发明人： James Mathew , Brett D. Lowe , Yunjun Ho , H. Jim Fulford , Jie Sun , Zhaoli Sun
IPC分类号： H01L21/76
CPC分类号： H01L29/0649 , H01L21/02164 , H01L21/022 , H01L21/02222 , H01L21/02271 , H01L21/02282 , H01L21/02326 , H01L21/02337 , H01L21/76229 , H01L27/11526 , H01L27/11573
摘要： A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.
摘要翻译：形成存储器阵列和外围电路隔离的方法包括在存储器阵列电路隔离沟槽的侧壁和在半导体材料中形成的外围电路隔离沟槽的化学气相沉积包含二氧化硅的衬垫。电介质材料流过含二氧化硅的衬垫以填充阵列隔离沟槽的剩余体积，并在至少一些外围隔离沟槽中的含二氧化硅的衬垫上形成电介质衬垫。电介质材料在不大于约500℃的温度下进行炉退火。退火的电介质材料被快速热处理至不低于约800℃的温度。含二氧化硅的材料经快速热化学气相沉积处理的介电材料以填充所述至少一些外围隔离沟槽的剩余体积。公开了其它方面，包括由公开的方法产生的集成电路和独立于制造方法的集成电路。

2. 发明授权

US06603180B1 Semiconductor device having large-area silicide layer and process of fabrication thereof 失效
标题翻译：具有大面积硅化物层的半导体器件及其制造方法
公开(公告)号：US06603180B1
公开(公告)日：2003-08-05
申请号：US08980380
申请日：1997-11-28
申请人： Mark I Gardner , H. Jim Fulford
发明人： Mark I Gardner , H. Jim Fulford
IPC分类号： H01L2976
CPC分类号： H01L29/517 , H01L21/28105 , H01L21/28194 , H01L29/51 , H01L29/665
摘要： A semiconductor device having a large-area silicide layer and fabrication method is provided. A semiconductor device, consistent with one embodiment of the invention, includes a silicon substrate, a gate insulating layer disposed over the silicon substrate, a gate electrode disposed over the gate insulating layer, and at least one active region disposed adjacent the gate electrode. Formed over the active region and in contact with the insulating layer is a silicide layer. The active region may, for example, be a source/drain region. The silicide layer generally has a surface area which is larger than that of conventional silicide layers. This, for example, reduces the resistance of the active regions of the semiconductor device and enhances device performance.
摘要翻译：提供了具有大面积硅化物层的半导体器件和制造方法。与本发明的一个实施例一致的半导体器件包括硅衬底，设置在硅衬底上的栅极绝缘层，设置在栅极绝缘层上的栅电极以及邻近栅电极设置的至少一个有源区。形成在有源区上并与绝缘层接触的是硅化物层。有源区可以例如是源/漏区。硅化物层通常具有比常规硅化物层大的表面积。例如，这降低了半导体器件的有源区的电阻并提高了器件性能。

3. 发明授权

US06552776B1 Photolithographic system including light filter that compensates for lens error 有权
标题翻译：光刻系统包括补偿透镜误差的滤光片
公开(公告)号：US06552776B1
公开(公告)日：2003-04-22
申请号：US09183176
申请日：1998-10-30
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
IPC分类号： G03B2754
CPC分类号： G03F7/70558 , G03F7/70191 , G03F7/706
摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.
摘要翻译：公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化数据以提供所需的光强度变化。本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

4. 发明授权

US06531364B1 Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer 有权
标题翻译：使用牺牲多晶硅种子层形成超薄栅极电介质的先进制造技术
公开(公告)号：US06531364B1
公开(公告)日：2003-03-11
申请号：US09129703
申请日：1998-08-05
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/518
摘要： A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.
摘要翻译：提出了一种用于形成晶体管的方法，其中多晶硅优选沉积在介电覆盖的衬底上以形成牺牲多晶硅层。然后可以将牺牲多晶硅层还原成所需的厚度。牺牲多晶硅层的厚度减少优选通过氧化牺牲多晶硅层的一部分然后蚀刻氧化部分进行。作为选择，可以加热牺牲多晶硅层使其重结晶。牺牲多晶硅层优选在含氮环境中退火，使得其被转换成包括氮化物的栅极电介质层。多晶硅可以沉积在栅极介电层上，并且可以去除多晶硅的部分以形成栅极导体。 LDD和源极/漏极区域可以形成在栅极导体附近。

5. 发明授权

US06500681B1 Run-to-run etch control by feeding forward measured metal thickness 失效
标题翻译：通过向前测量的金属厚度进行运行蚀刻控制
公开(公告)号：US06500681B1
公开(公告)日：2002-12-31
申请号：US10044642
申请日：2002-01-11
申请人： Craig William Christian , H. Jim Fulford
发明人： Craig William Christian , H. Jim Fulford
IPC分类号： H01L2100
CPC分类号： H01L21/67253 , H01L22/26
摘要： Disclosed herein is a method comprised of forming a metal layer above a structure layer on a workpiece, measuring a thickness of the metal layer, determining, based upon the measured thickness of the metal layer, at least one parameter of an etching process to be performed on the metal layer, and performing the etching process comprised of the determined parameter on the metal layer. Also disclosed is a system comprised of a deposition tool for forming a metal layer above a structure layer on a workpiece, a metrology tool for measuring a thickness of the metal layer, a controller for determining, based upon the measured thickness of the metal layer, at least one parameter of an etch process to be performed on the metal layer, and an etch tool adapted to perform an etch process comprised of the determined parameter on the metal layer.
摘要翻译：本文公开了一种方法，包括在工件上的结构层上形成金属层，测量金属层的厚度，基于所测量的金属层的厚度，确定要执行的蚀刻工艺的至少一个参数并且在金属层上执行由确定的参数构成的蚀刻工艺。还公开了一种系统，包括用于在工件上形成结构层上方的金属层的沉积工具，用于测量金属层的厚度的计量工具，用于基于所测量的金属层厚度确定的控制器，要在金属层上执行的蚀刻工艺的至少一个参数，以及适于在金属层上执行由确定的参数构成的蚀刻工艺的蚀刻工具。

6. 发明授权

US06454899B1 Apparatus for filling trenches 有权
标题翻译：用于填充沟槽的装置
公开(公告)号：US06454899B1
公开(公告)日：2002-09-24
申请号：US09885455
申请日：2001-06-19
申请人： William J. Campbell , H. Jim Fulford , Christopher H. Raeder , Craig W. Christian , Thomas Sonderman
发明人： William J. Campbell , H. Jim Fulford , Christopher H. Raeder , Craig W. Christian , Thomas Sonderman
IPC分类号： H01L2100
CPC分类号： H01L22/20 , H01L21/76229
摘要： A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.
摘要翻译：提供了一种用于填充沟槽的方法。提供了至少形成有第一层的晶片。在第一层中形成沟槽。测量沟槽的深度。基于沟槽的深度确定目标厚度。在沟槽上形成第二层目标厚度。处理线包括沟槽蚀刻工具，第一计量工具，沟槽填充工具和自动过程控制器。沟槽蚀刻工具适于在晶片上的第一层中形成沟槽。第一个计量工具适用于测量沟槽的深度。沟槽填充工具适于基于操作配方在第一层上形成第二层。自动过程控制器适于基于沟槽的深度确定目标厚度，并且基于目标厚度修改沟槽填充工具的操作配方。

7. 发明授权

US06303962B1 Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures 有权
标题翻译：具有低电阻金属源和漏极的绝缘隔离晶体管，使用牺牲源极和漏极结构形成
公开(公告)号：US06303962B1
公开(公告)日：2001-10-16
申请号：US09227512
申请日：1999-01-06
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： A01L2701
CPC分类号： H01L29/66757 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/78675
摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysilicon layer arranged over a dielectric layer on a semiconductor substrate. To fabricate the transistor, an isolating dielectric, polysilicon layer, and protective dielectric layer are deposited over a semiconductor substrate. Source/drain trenches are formed in the protective dielectric and polysilicon layers and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which may be formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operation speed.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。晶体管的栅极也可以由诸如金属的低电阻材料形成。晶体管沟道位于布置在半导体衬底上的电介质层上的多晶硅层中。为了制造晶体管，在半导体衬底上沉积隔离电介质，多晶硅层和保护电介质层。源极/漏极沟槽形成在保护电介质层和多晶硅层中，随后填充有牺牲电介质。位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。随后去除牺牲电介质并用可由低电阻金属形成的源极/漏极区域代替。所得到的晶体管可以表现出低接触和串联电阻，并且增加了操作速度。

8. 发明授权

US06255698B1 Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit 有权
标题翻译：在集成电路中分别优化了n沟道和p沟道晶体管的栅极结构
公开(公告)号：US06255698B1
公开(公告)日：2001-07-03
申请号：US09301263
申请日：1999-04-28
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L29/66545
摘要： An integrated circuit containing separately optimized gate structures for n-channel and p-channel transistors is provided and formed. Original gate structures for both n-channel and p-channel transistors are patterned over appropriately-doped active regions of a semiconductor substrate. Protective dielectrics are formed over the semiconductor substrate to the same elevation level as the upper surfaces of the original gate structures, so that only the upper surfaces of the gate structures are exposed. A masking layer is used to cover the gate structures of either the p-channel or the n-channel transistors. The uncovered gate structures are removed, forming a trench within the protective dielectric in place of each removed gate structure. The trenches are refilled with a new gate structure which is preferably optimized for operation of the appropriate transistor type (n-channel or p-channel).
摘要翻译：提供并形成了包含用于n沟道和p沟道晶体管的单独优化的栅极结构的集成电路。用于n沟道和p沟道晶体管的原始栅极结构在半导体衬底的适当掺杂的有源区上被图案化。在半导体衬底上形成与原始栅极结构的上表面相同的高度水平面的保护电介质，使得只有栅极结构的上表面露出。掩模层用于覆盖p沟道或n沟道晶体管的栅极结构。去除未覆盖的栅极结构，在保护电介质内形成沟槽，代替每个去除的栅极结构。沟槽用新的栅极结构重新填充，该栅极结构优选地适合于适当的晶体管类型（n沟道或p沟道）的操作。

9. 发明授权

US06245649B1 Method for forming a retrograde impurity profile 有权
标题翻译：形成逆行杂质分布的方法
公开(公告)号：US06245649B1
公开(公告)日：2001-06-12
申请号：US09251923
申请日：1999-02-17
申请人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
发明人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L2104
CPC分类号： H01L29/105 , H01L21/2652
摘要： A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.
摘要翻译：提供了一种在半导体衬底中形成逆向杂质分布的方法。该方法包括在半导体衬底的表面上形成具有在大约至大约的范围内的厚度的牺牲层。此后，进行离子注入工艺，其中掺杂杂质离子在有效地在半导体衬底中形成逆向杂质分布的条件下引导通过牺牲层并进入半导体衬底。

10. 发明授权

US06239467B1 Method of forming semiconductor devices using gate electrode length and spacer width for controlling drive current strength 有权
标题翻译：使用栅电极长度和间隔物宽度形成半导体器件以控制驱动电流强度的方法
公开(公告)号：US06239467B1
公开(公告)日：2001-05-29
申请号：US09183616
申请日：1998-10-30
申请人： Mark I. Gardner , H. Jim Fulford , Anthony Toprac
发明人： Mark I. Gardner , H. Jim Fulford , Anthony Toprac
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L22/20 , H01L29/6656 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： A semiconductor device having a controlled drive current strength is produced by varying spacer width to accommodate any variation in gate electrode length from a desired value. After formation of the gate electrode on a substrate, the length is measured and compared to a desired value. Based on any differences between the measured and desired values, the width of spacer is determined in order to counteract the variation in gate electrode length. This results in maintaining the desired channel length after dopant implanting, to provide the desired drive current strength. The present process permits close control over the drive current strength of semiconductor devices and also decreased variation within and between lots and corresponding increases in productivity.
摘要翻译：具有受控的驱动电流强度的半导体器件通过改变间隔物宽度来产生，以适应栅电极长度与期望值的任何变化。在基板上形成栅电极之后，测量长度并将其与期望值进行比较。基于测量值和期望值之间的任何差异，确定间隔物的宽度以抵消栅电极长度的变化。这导致在掺杂剂注入之后保持期望的沟道长度，以提供期望的驱动电流强度。本方法允许对半导体器件的驱动电流强度进行密切控制，并且还可以减少批次之间和批量之间的变化，并且相应地提高生产率。

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