专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08482994B2 Semiconductor device having resistance based memory array, method of reading, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，读取方法和与其相关联的系统的半导体器件
公开(公告)号：US08482994B2
公开(公告)日：2013-07-09
申请号：US13064476
申请日：2011-03-28
申请人： Kwang-Jin Lee , Du Eung Kim , Yong Jun Lee
发明人： Kwang-Jin Lee , Du Eung Kim , Yong Jun Lee
IPC分类号： G11C11/34
CPC分类号： G11C13/0061 , G11C7/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/004
摘要： One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.
摘要翻译：一个实施例包括非易失性存储单元阵列和被配置为在非易失性存储单元阵列中写入数据之后的一段时间内禁止非易失性存储单元阵列的读操作的读单元。

2. 发明授权

US08305806B2 Nonvolatile memory device and method for controlling word line or bit line thereof 有权
标题翻译：用于控制字线或其位线的非易失性存储器件和方法
公开(公告)号：US08305806B2
公开(公告)日：2012-11-06
申请号：US12659690
申请日：2010-03-17
申请人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
发明人： Joon-Yong Choi , Byunggil Choi , Yu Hwan Ro , Yong-Jun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/08
摘要： A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.
摘要翻译：非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。本地线分别对应于全局选择线。第一选择电路被配置为连接到全局选择线以选择全局选择线。第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

3. 发明授权

US08194492B2 Variable resistance memory device and system 有权
标题翻译：可变电阻存储器件和系统
公开(公告)号：US08194492B2
公开(公告)日：2012-06-05
申请号：US12693005
申请日：2010-01-25
申请人： Qi Wang , Kwang-Jin Lee , Woo-Yeong Cho , Taek-Sung Kim , Kwang-Ho Kim , Hyun-Ho Choi , Yong-Jun Lee , Hye-Jin Kim
发明人： Qi Wang , Kwang-Jin Lee , Woo-Yeong Cho , Taek-Sung Kim , Kwang-Ho Kim , Hyun-Ho Choi , Yong-Jun Lee , Hye-Jin Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C11/005 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C16/0483 , G11C2013/0078 , G11C2213/71
摘要： Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.
摘要翻译：公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

4. 发明申请

US20110179237A1 Semiconductor device having resistance based memory array, method of reading, and systems associated therewith 有权
标题翻译：具有基于电阻的存储器阵列，读取方法和与其相关联的系统的半导体器件
公开(公告)号：US20110179237A1
公开(公告)日：2011-07-21
申请号：US13064476
申请日：2011-03-28
申请人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
发明人： Kwang Jin Lee , Du Eung Kim , Yong Jun Lee
IPC分类号： G06F12/00
CPC分类号： G11C13/0061 , G11C7/04 , G11C8/06 , G11C8/10 , G11C8/12 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/00 , G11C13/0004 , G11C13/004
摘要： One embodiment includes a non-volatile memory cell array, and a read unit configured to disable read operation for the non-volatile memory cell array for a time period following writing of data in the non-volatile memory cell array.
摘要翻译：一个实施例包括非易失性存储单元阵列和被配置为在非易失性存储单元阵列中写入数据之后的一段时间内禁止非易失性存储单元阵列的读操作的读单元。

5. 发明授权

US07563667B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07563667B2
公开(公告)日：2009-07-21
申请号：US12002241
申请日：2007-12-13
申请人： Choul Joo Ko , Yong Jun Lee
发明人： Choul Joo Ko , Yong Jun Lee
IPC分类号： H01L21/8234 , H01L21/8244 , H01L21/8242 , H01L21/336
CPC分类号： H01L27/0629 , H01L28/40
摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.
摘要翻译：在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，并且在器件隔离层上形成底电极和电介质层。绝缘侧壁形成在底部电极的两侧。在电介质层上形成顶部电极，同时在硅衬底的晶体管区域形成栅电极。源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

6. 发明申请

US20080176370A1 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080176370A1
公开(公告)日：2008-07-24
申请号：US12002241
申请日：2007-12-13
申请人： Choul Joo Ko , Yong Jun Lee
发明人： Choul Joo Ko , Yong Jun Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/0629 , H01L28/40
摘要： In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.
摘要翻译：在形成半导体器件的方法中，在硅衬底的电容器区域中形成器件隔离层，在器件隔离层上形成底部电极和电介质层。绝缘侧壁形成在底部电极的两侧。在电介质层上形成顶部电极，同时在硅衬底的晶体管区域中形成栅电极。源极/漏极杂质区域形成在栅极电极两侧的硅衬底中。

7. 发明申请

US20070184610A1 INTEGRATED CIRCUIT CAPACITOR STRUCTURE 失效
公开(公告)号：US20070184610A1
公开(公告)日：2007-08-09
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

8. 发明授权

US07154162B2 Integrated circuit capacitor structure 有权
公开(公告)号：US07154162B2
公开(公告)日：2006-12-26
申请号：US10678531
申请日：2003-10-03
申请人： Jeong-Hoon Ahn , Kyungtae Lee , Mu-Kyung Jung , Yong-Jun Lee
发明人： Jeong-Hoon Ahn , Kyungtae Lee , Mu-Kyung Jung , Yong-Jun Lee
IPC分类号： H01L29/00
CPC分类号： H01L28/55 , H01L21/76895 , H01L23/5223 , H01L27/0805 , H01L27/1085 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

9. 发明授权

US06987173B2 Process for the preparation of active somatotropin from inclusion bodies 失效
公开(公告)号：US06987173B2
公开(公告)日：2006-01-17
申请号：US09811789
申请日：2001-01-12
申请人： Yong-Jun Lee , Hong-Kyun Lee , Kyuboem Han
发明人： Yong-Jun Lee , Hong-Kyun Lee , Kyuboem Han
IPC分类号： C07K3/08
CPC分类号： C07K1/1133 , C07K14/61 , Y10S530/824 , Y10S530/825
摘要： A process for the preparation of biologically active somatotropin from inclusion bodies of a recombinant host cell containing an inactive form of said somatotropin protein comprises the steps of: (a) contacting the inclusion bodies with an aqueous alcohol solution at an alkaline pH to solubilize said protein; and (b) bringing the solubilized protein into contact with a mild oxidizing agent to refold and form intramolecular disulfide bonds between cysteine residues of said protein.

10. 发明申请

US20050026422A1 Method of forming an insulating structure having an insulating interlayer and a capping layer and method of forming a metal wiring structure using the same 失效
标题翻译：形成具有绝缘中间层和覆盖层的绝缘结构的方法和使用其形成金属布线结构的方法
公开(公告)号：US20050026422A1
公开(公告)日：2005-02-03
申请号：US10899934
申请日：2004-07-27
申请人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
发明人： Yoon-Hae Kim , Kyung-Tae Lee , Yong-Jun Lee
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/336 , H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02362 , H01L21/3122 , H01L21/31629 , H01L21/31633 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： In a method of forming an insulating structure, an insulating interlayer is formed on a substrate using a silicon source gas and a reaction gas. A capping layer is formed in-situ on the insulating interlayer by increasing a flow rate of an oxidizing gas included in the reaction gas so that the capping layer has a second thickness when the insulating interlayer is formed on the substrate to have a first thickness. The insulating structure dose not have an interface between the insulating interlayer and the capping layer so that the insulating interlayer is not subject to damage by a cleaning solution during a subsequent cleaning process, since the cleaning solution maynot permeate into the insulating structure. Additionally, leakage current is mitigated or eliminated between the insulating interlayer and the capping layer, thereby improving the reliability of a semiconductor device including the insulating structure.
摘要翻译：在形成绝缘结构的方法中，使用硅源气体和反应气体在基板上形成绝缘中间层。通过增加反应气体中包含的氧化气体的流量，在绝缘中间层上原位形成覆盖层，使得当在基板上形成绝缘中间层以具有第一厚度时，覆盖层具有第二厚度。绝缘结构在绝缘中间层和覆盖层之间不具有界面，使得在随后的清洁过程中绝缘中间层不被清洁溶液损坏，因为清洁溶液可能不渗透到绝缘结构中。此外，在绝缘中间层和覆盖层之间减轻或消除泄漏电流，从而提高包括绝缘结构的半导体器件的可靠性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式