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1. 发明授权

US06855629B2 Method for forming a dual damascene wiring pattern in a semiconductor device 有权
标题翻译：在半导体器件中形成双镶嵌布线图案的方法
公开(公告)号：US06855629B2
公开(公告)日：2005-02-15
申请号：US10437529
申请日：2003-05-14
申请人： Jae-Hak Kim , Soo-Geun Lee , Wan-Jae Park , Kyoung-Woo Lee
发明人： Jae-Hak Kim , Soo-Geun Lee , Wan-Jae Park , Kyoung-Woo Lee
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808
摘要： In a method for forming a dual damascene wiring pattern, an etch stop film and an interlayer dielectric film comprising an SiOC:H group material are formed on a substrate having an electrical connection layer formed thereon. An anti-reflection layer is formed on the interlayer dielectric film. A primary opening is formed by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film. A sacrificial film is formed comprising a low dielectric constant material in the primary opening and on the anti-reflection layer. A trench photoresist pattern having a width larger than that of the primary opening is formed on the sacrificial film after plasma-processing the sacrificial film. The sacrificial film, the anti-reflection layer and the interlayer dielectric film are sequentially etched using the trench photoresist pattern as an etch mask so as to form a secondary opening of a trench shape, and the trench photoresist pattern is removed, said secondary opening extending from an upper portion of the primary opening. The sacrificial film remaining is removed, the exposed etch stop film and anti-reflection layer are removed, the primary and secondary openings are filled with metal so as to be electrically coupled with the electrical connection layer. In this manner, damage to the etch stop layer is mitigated or eliminated during processing.
摘要翻译：在形成双镶嵌布线图案的方法中，在其上形成有电连接层的基板上形成蚀刻停止膜和包含SiOC:H基材料的层间电介质膜。在层间电介质膜上形成防反射层。通过蚀刻抗反射层和层间电介质膜形成初级开口以暴露蚀刻停止膜的表面。在初级开口和抗反射层中形成包括低介电常数材料的牺牲膜。在等离子体处理牺牲膜之后，在牺牲膜上形成具有大于初级开口的宽度的沟槽光致抗蚀剂图案。使用沟槽光致抗蚀剂图案作为蚀刻掩模，依次蚀刻牺牲膜，抗反射层和层间电介质膜，以形成沟槽形状的次级开口，并移除沟槽光致抗蚀剂图案，所述次级开口延伸从主开口的上部。去除残留的牺牲膜，去除暴露的蚀刻停止膜和抗反射层，用金属填充初级和次级开口以与电连接层电耦合。以这种方式，在处理期间减轻或消除对蚀刻停止层的损伤。

2. 发明授权

US06849536B2 Inter-metal dielectric patterns and method of forming the same 失效
标题翻译：金属间电介质图案及其形成方法
公开(公告)号：US06849536B2
公开(公告)日：2005-02-01
申请号：US10404210
申请日：2003-04-01
申请人： Soo-Geun Lee , Ju-Hyuk Chung , Il-Goo Kim , Kyoung-Woo Lee , Wan-Jae Park , Jae-Hak Kim
发明人： Soo-Geun Lee , Ju-Hyuk Chung , Il-Goo Kim , Kyoung-Woo Lee , Wan-Jae Park , Jae-Hak Kim
IPC分类号： H01L21/28 , H01L21/316 , H01L21/768 , H01L21/4762
CPC分类号： H01L21/76831 , H01L21/316 , H01L21/31612 , H01L21/31629 , H01L21/31633 , H01L21/31695 , H01L21/76808 , H01L21/76835 , H01L2221/1036
摘要： Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection. Then, an upper capping layer is formed on the entire surface of the semiconductor substrate including the via hole. The upper capping layer and the upper dielectric layer are successively patterned to form a trench line exposing the upper side of the via hole. The upper capping layer is formed of at least one material selected from the group consisting of a silicon oxide layer, a silicon carbide layer, a silicon nitride layer, and a silicon oxynitride layer, by using PECVD.
摘要翻译：提供了金属间介电图案及其形成方法。该图案包括布置在半导体衬底上的下部互连，具有通孔暴露下部互连并覆盖半导体衬底的下部电介质图案和下部封盖图案的下部电介质层，沟槽线暴露通孔并依次堆叠在下介电层上。下电介质层和上电介质图案是由诸如SiO 2，SiOF，SiOC和多孔电介质的材料形成的低K电介质层。该方法包括在形成在半导体衬底上的下互连件上依次层叠包括下电介质层和上电介质层的金属间电介质层。图案化金属间电介质层以形成通孔，其暴露下部互连的上侧。然后，在包括通孔的半导体衬底的整个表面上形成上覆盖层。上覆盖层和上电介质层被连续地图案化以形成暴露通孔上侧的沟槽线。通过使用PECVD，上覆盖层由选自氧化硅层，碳化硅层，氮化硅层和氮氧化硅层的至少一种材料形成。

3. 发明授权

US07560332B2 Integrated circuit capacitor structure 失效
标题翻译：集成电路电容器结构
公开(公告)号：US07560332B2
公开(公告)日：2009-07-14
申请号：US11733711
申请日：2007-04-10
申请人： Kyoung-Woo Lee , Wan-Jae Park , Jeong-Hoon Ahn , Kyung-Tae Lee , Mu-Kyeng Jung , Yong-Jun Lee , Il-Goo Kim , Soo-Geun Lee
发明人： Kyoung-Woo Lee , Wan-Jae Park , Jeong-Hoon Ahn , Kyung-Tae Lee , Mu-Kyeng Jung , Yong-Jun Lee , Il-Goo Kim , Soo-Geun Lee
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.
摘要翻译：本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

4. 发明授权

US07033944B2 Dual damascene process 有权
标题翻译：双镶嵌工艺
公开(公告)号：US07033944B2
公开(公告)日：2006-04-25
申请号：US10654770
申请日：2003-09-04
申请人： Wan-Jae Park , Il-Goo Kim , Sang-Rok Hah , Kyoung-Woo Lee
发明人： Wan-Jae Park , Il-Goo Kim , Sang-Rok Hah , Kyoung-Woo Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/76808
摘要： A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.
摘要翻译：公开了一种双镶嵌工艺。根据本发明的双镶嵌工艺，通过金属间电介质层的第一凹陷区域填充有底部保护层，同时蚀刻底部保护层和金属间电介质层，以形成第二凹陷区域，该凹陷区域具有通过使用蚀刻气体相对于底部保护层选择性地蚀刻金属间电介质层，比第一凹陷区域上的第一凹陷区域更浅的深度和更宽的宽度。换句话说，相对于底部保护层的蚀刻选择比，金属间电介质层优选为约0.5至约1.5。因此，可以形成双重镶嵌结构而不形成副产物或氧化物栅栏。

5. 发明申请

US20060024971A1 Dry etching method using polymer mask selectively formed by CO gas 审中-公开
标题翻译：使用由CO气体选择性形成的聚合物掩模的干蚀刻方法
公开(公告)号：US20060024971A1
公开(公告)日：2006-02-02
申请号：US11193199
申请日：2005-07-29
申请人： Wan-Jae Park , Ho-Sen Chang , Young-Mook Oh
发明人： Wan-Jae Park , Ho-Sen Chang , Young-Mook Oh
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/76802 , H01L21/0273 , H01L21/3081 , H01L21/3085 , H01L21/31144 , H01L21/32139 , H01L2221/1057
摘要： A dry etching method comprises placing a semiconductor substrate in a reactor, the semiconductor substrate comprising a photoresist pattern formed on an etching target layer, supplying carbon monoxide gas into the reactor to selectively deposit polymer on the photoresist pattern to form a polymer layer, and etching the etching target layer using the photoresist pattern and the polymer layer as an etch mask.
摘要翻译：干蚀刻方法包括将半导体衬底放置在反应器中，所述半导体衬底包括形成在蚀刻靶层上的光致抗蚀剂图案，将一氧化碳气体供应到反应器中，以选择性地将聚合物沉积在光致抗蚀剂图案上以形成聚合物层，并且蚀刻使用光致抗蚀剂图案的蚀刻目标层和作为蚀刻掩模的聚合物层。

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