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1. 发明专利

JP2003031629A Method and apparatus for testing pattern 审中-公开
标题翻译：测试模式的方法和装置
公开(公告)号：JP2003031629A
公开(公告)日：2003-01-31
申请号：JP2001216254
申请日：2001-07-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HIROI TAKASHI , WATANABE MASAHIRO , TANAKA MAKI , KUNI TOMOHIRO , SHISHIDO CHIE , NISHIYAMA HIDETOSHI , OKUDA HIROTO , MIYAI YASUSHI , GUNJI YASUHIRO , SHIMODA ATSUSHI , OSHIMA YOSHIMASA
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To eliminate the problem that in a method wherein a charged particle beam is cast on a substrate to be tested, and secondary electrons or the like emitted are detected to obtain an image, and then the obtained image is compared with a reference image to test the substrate for pattern defects or a defect is checked by moving to a location of a pattern defect, the substrate to be tested is charged up by the irradiation of the charged particle beam, causing the charged particle beam to be bent and then the positional deviation of the defect.
SOLUTION: An amount of positional deviation at the time of inspection and an amount of positional deviation from a reference image are inspected and, at the same time, calculated to correct the location of the defect at the time of inspection. Defects information is added with an image at the time of inspection, and then is corrected for an amount of positional deviation between image information and layout information. The defects information is added with the image at the time of inspection, and then is compared with an image at the time of checking defects to correct the location of the defect. When checking defects, an image is obtained and then is added to the defects information, and the defects information is compared with the image at the time of checking defects and an image detected by another apparatus or with the layout information, to correct the location of the defect.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了消除在被测试的基板上投射带电粒子束的方法，并且检测发射的二次电子等以获得图像的问题，然后将获得的图像与通过移动到图案缺陷的位置来检查用于图案缺陷的基板的参考图像或缺陷，通过照射带电粒子束对待测试的基板进行充电，使带电粒子束弯曲，那么缺陷的位置偏差。解决方案：检查检查时的位置偏差量和与参考图像的位置偏差量，同时计算出在检查时纠正缺陷的位置。缺陷信息在检查时添加图像，然后对图像信息和布局信息之间的位置偏差量进行校正。缺陷信息在检查时与图像一起添加，然后与检查缺陷时的图像进行比较，以校正缺陷的位置。当检查缺陷时，获得图像，然后将其添加到缺陷信息中，并且在检查缺陷时的缺陷信息和与其他装置检测到的图像或布局信息相比较时，将缺陷信息与图像进行比较，以校正缺陷。

2. 发明专利

JP2004077165A Defect classification method and its device 有权
公开(公告)号：JP2004077165A
公开(公告)日：2004-03-11
申请号：JP2002234302
申请日：2002-08-12
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OKUDA HIROTO , HONDA TOSHIFUMI , TAKAGI YUJI , MIYAMOTO ATSUSHI
IPC分类号： G01N21/88 , G01N21/956 , G06T1/00 , G06T7/00
CPC分类号： G06T7/001
摘要： PROBLEM TO BE SOLVED: To provide a method that automatically classifies images of defects occurring in surfaces of a semiconductor electronic circuit substrate or the like, does not need to collect much teaching data, can flexibly respond to different defect classifying requests depending on users, and has high reliability, and to provide its device.
SOLUTION: A user defines classification class constitution by arbitrarily combining a class provided by a system or a class defined by the user. Additionally, the user provides prior knowledge about a defect class as a constraint, and learning with the constraint is performed.
COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2003023056A Method for sorting defect of semiconductor device, method for predicting yield of the semiconductor device, method for manufacturing the semiconductor device, defect-sorting system of semiconductor device and semiconductor device-sorting apparatus, and program used therefor and recording medium 审中-公开
标题翻译：用于分割半导体器件的缺陷的方法，用于预测半导体器件的形成的方法，用于制造半导体器件的方法，半导体器件的缺陷分配系统和半导体器件分离器件，以及用于其和记录介质的程序
公开(公告)号：JP2003023056A
公开(公告)日：2003-01-24
申请号：JP2001209741
申请日：2001-07-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HAMAMURA YUICHI , SUGIMOTO ARITOSHI , OKUDA HIROTO
IPC分类号： G01R31/02 , G01N21/956 , G01R31/302 , G06T1/00 , G06T7/00 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To execute an accurate defect fatalness evaluation, a yield prediction and a fault position specification in an in-line defect checking step.
SOLUTION: A method for sorting defects of a semiconductor device comprises steps of extracting a wiring position which becomes a fault candidate by superposing layout pattern data of a semiconductor chip with a defecting image, discriminating wirings of the extracted fault candidate according to a wiring function type, and sorting a short-circuit mode type, a disconnection mode type or the like according to a wiring fault mode type.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：在线缺陷检查步骤中执行准确的缺陷致命性评估，成品率预测和故障位置指定。解决方案：一种用于分类半导体器件的缺陷的方法包括以下步骤：通过用缺陷图像叠加具有半导体芯片的布局图案数据来提取成为故障候选的布线位置，根据布线功能类型识别所提取的故障候选的布线，并根据布线故障模式类型对短路模式类型，断开模式类型等进行排序。

4. 发明专利

JP2002323458A DEFECT INSPECTION MANAGEMENT SYSTEM AND DEFECT INSPECTION SYSTEM AND APPARATUS OF ELECTRONIC CIRCUIT PATTERN 审中-公开
公开(公告)号：JP2002323458A
公开(公告)日：2002-11-08
申请号：JP2001294482
申请日：2001-09-26
申请人： HITACHI LTD
发明人： OKUDA HIROTO , TAKAGI YUJI , OSHIMA YOSHIMASA , ONO MAKOTO , WATANABE MASAHIRO , MAEDA SHUNJI , NOGUCHI MINORU
IPC分类号： G01B11/00 , G01B11/30 , G01N21/95 , G01N21/956 , G01N23/225 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To inspect a region to be inspected locally under optimum inspection conditions for reducing false reports and inspection time, and to avoid the explosion of the number of detection defects for easily controlling fatal detects. SOLUTION: All-purpose layout data used for creating the mask of a semiconductor wafer are stored into a design information server 2, the layout data are referred to for dividing the region to be inspected by a pattern inspection device 1 into the partial inspection regions of cell and non-cell sections, and an inspection parameter is set for each partial inspection region. A defect review apparatus 8 takes in an inspection result by the pattern inspection apparatus 1. In this case, when a defect image is to be taken in, the defect review apparatus 8 judges at which section of the cell and non-cell sections, a pattern congestion section, and the like the defect occurs based on the layout data. According to the judged result, the inspection parameter such as the shooting multiple of the defect is set, and a fatal control standard is set.

5. 发明专利

JP2002042111A PATTERN INSPECTING METHOD AND ITS SYSTEM 失效
公开(公告)号：JP2002042111A
公开(公告)日：2002-02-08
申请号：JP2000231388
申请日：2000-07-27
申请人： HITACHI LTD
发明人： OKUDA HIROTO , KOSHISHIBA HIROYA , KOBAYASHI IRARIO HARUOMI
IPC分类号： G01B11/24 , G01N21/956 , G06T1/00 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To solve problems that an image process by hardware in the conventional pattern inspecting system requires the design and manufacture of a dedicated electronic circuit, resulting in a long development period and a high development cost, although the processing speed can be made very high, and the image process by software requires a tremendous memory capacity and a long processing period, thus an applicable object is limited. SOLUTION: Compressed image data are generated from flawless reference image data by using a run length coding system, for example, and stored in the memory of a personal computer. A detection image by a sensor is transferred to the memory of the personal computer from a personal computer having an image input function, and a flaw is extracted from the detection image by a software process on the personal computer without deploying the compressed image data.

6. 发明专利

JP2002124555A SEM-TYPE DEFECT-REVIEWING DEVICE AND METHOD AND INSPECTION SYSTEM 失效
公开(公告)号：JP2002124555A
公开(公告)日：2002-04-26
申请号：JP2000316334
申请日：2000-10-17
申请人： HITACHI LTD
发明人： OKUDA HIROTO , TAKAGI YUJI , SHIBUYA HISAE , NAKAGAKI AKIRA , KUROSAKI TOSHISHIGE , OBARA KENJI
IPC分类号： G01N23/225 , H01J37/22 , H01J37/28 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide an SEM-type defect-reviewing device that automatically classifies defects in continuity fail such as discontinuity and short-circuiting generated in conductor components such as a contact hole buried in a substrate to be inspected such as a semiconductor wafer to categories correlating closely with the causes of the defect. SOLUTION: Potential contrast defects are classified according to the arrangement state of the defect holes, or are classified based on the correlation with a component position in a preprocess by referring to design information. In addition, the cause of defect is estimated.

7. 发明专利

JP2001249013A SOLID SHAPE DETECTOR AND PATTERN INSPECTION DEVICE AND THEIR METHOD 失效
公开(公告)号：JP2001249013A
公开(公告)日：2001-09-14
申请号：JP2000062155
申请日：2000-03-07
申请人： HITACHI LTD
发明人： OKUDA HIROTO , KOSHISHIBA HIROYA
IPC分类号： G01B11/245 , G01B11/24
摘要： PROBLEM TO BE SOLVED: To speedily and accurately detect a solid shape of wiring pattern of electronic circuit substrate and the like without any blind spot. SOLUTION: A reflection beam group of a plurality of irradiation beams from an inspection object 11 is equally separated into a reflection beam groups L1, L2, L3 and L4. A plurality of reflection beam of the reflection beam group L1 are focused with an imagery lens 22 and are received with individual cells of a line sensor 30 by way of each pin hole of a pin hole array 26. Similarly in the beam groups L2, L3 and L4, a plurality of reflection beams are focused with imagery lenses 23 to 25 and are received with individual cells of line sensors 31 to 33 by way of each pin hole of pin hole arrays 27 to 29. The pin hole arrays 26 to 29 have different positions shared with the detection object 11, and the height at beam irradiation point of the inspection object 11 is detected from the detection output of the cells receiving the reflection beams against the same irradiation beams of the line sensors 31 to 33.

8. 发明专利

JP2001124530A METHOD AND APPARATUS FOR DETECTING SOLID SHAPE AND METHOD AND APPARATUS FOR INSPECTION 失效
公开(公告)号：JP2001124530A
公开(公告)日：2001-05-11
申请号：JP30561499
申请日：1999-10-27
申请人： HITACHI LTD
发明人： KOSHISHIBA HIROYA , OKUDA HIROTO , HONDA TOSHIFUMI , ISOBE MITSUNOBU , YOSHIMURA KAZUSHI , KOBAYASHI HARUOMI
IPC分类号： G01B11/24 , G01B11/06 , G01B11/245
摘要： PROBLEM TO BE SOLVED: To inspect the solid shape of an object under inspection with high accuracy and at high speed. SOLUTION: A slit light illuminates an object 1 under inspection through an objective 15, a reflected light from the irradiated region is reflected by a perforated mirror 14 and branched by beam splitters 18a, 18b on three optical paths, after passing through an aperture restriction 16 and an image-forming lens 17. Line sensors 7a, 7b are provided for each branch optical path, the line sensor 7a is disposed in front of the focal plane, the line sensor 7b is disposed behind the focal plane, the line sensors 7a, 7b are positionally adjusted so that n-th detection pixels of the sensors 7a, 7b receive the image of n-th unit regions on the slit light irradiated region of the object 1, the defocus quantity of the images on the planes of the light sensors 7a, 7b differs, depending on the unit region height on the slit light irradiated region of the object 1 and cells of the light sensors 7a, 7b detect the light quantity, corresponding to the defocus quantity.

9. 发明专利

JP2000046748A METHOD AND APPARATUS FOR INSPECTING CONDUCTOR PATTERN AND PRODUCTION OF MULTILAYERED SUBSTRATE 失效
公开(公告)号：JP2000046748A
公开(公告)日：2000-02-18
申请号：JP21155998
申请日：1998-07-27
申请人： HITACHI LTD
发明人： KOSHISHIBA HIROYA , ISOBE MITSUNOBU , NOMOTO MINEO , KOBAYASHI HARUOMI , IRIE YOKO , OKUDA HIROTO , SENGOKU NORIO , MIO SHIGEMI
IPC分类号： G01B11/30 , G01N21/88 , G01N21/956 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a conductor pattern inspecting method and apparatus capable of performing inspection certainly at a high speed, and a method for producing a multilayered substrate. SOLUTION: A circuit board 51 to be inspected is illuminated by polarized illumination light having a wavelength of 300-550 nm, and the optical image based on reflected light blocking the polarizing component of the polarized illumination light from the illuminated circuit board to be inspected is detected by a detector to be converted to an optical image signal. The converted optical image signal is binarized on the basis of a predetermined threshold value to be converted to a binary image signal showing a conductor pattern, the positional shift quantity of the conductor pattern is calculated on the basis of the binary image signal showing the converted conductor pattern, and alignment is performed on the basis of the positional shift quantity of the conductor pattern to be compared to extract the defect of the conductor pattern.

10. 发明专利

JPH11351836A SOLID SHAPE DETECTING DEVICE AND METHOD THEREOF 失效
公开(公告)号：JPH11351836A
公开(公告)日：1999-12-24
申请号：JP15881198
申请日：1998-06-08
申请人： HITACHI LTD
发明人： OKUDA HIROTO , HONDA TOSHIFUMI
IPC分类号： G01B11/24 , G01B11/245
摘要： PROBLEM TO BE SOLVED: To reduce an adjusting work time that takes matching between images by setting values in necessary characteristics such as a gain of each detector determined in advance of working using a calibration sample, at each compensation means. SOLUTION: A solid shape detecting device inspecting a lead soldering part of an electronic part based upon imaging formation information is provided with amplifiers 122, 123, 124 with multistage method that can control a gain. An offset compensating value of each amplifier is set from outputs of optical detectors 119, 120, 121 when predetermined calculation sample is placed at XYZ stage 102 and light radiation intensity is set at zero, and also a gain of each amplifier is set from an output of each optical detector in the case of travelling a detecting height. Thereby, an output signal intensity when each light detector and a detecting object 101 are placed at a conjugate location to a detecting optical system is normalized. A compensation quantity for position deviation is calculated when the method is applied to the shape from focus method and compensation quantity for focus position is calculated the confocal method is employed.

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