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1. 发明授权

US07627044B2 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US07627044B2
公开(公告)日：2009-12-01
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

2. 发明申请

US20070098112A1 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US20070098112A1
公开(公告)日：2007-05-03
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04L27/04 , H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

3. 发明授权

US07295578B1 Method and apparatus for synchronizing auxiliary data and video data transmitted over a TMDS-like link 有权
标题翻译：用于同步辅助数据和通过类似TMDS的链路传输的视频数据的方法和装置
公开(公告)号：US07295578B1
公开(公告)日：2007-11-13
申请号：US09954291
申请日：2001-09-12
申请人： James D. Lyle , Gyudong Kim , Min-Kyu Kim , Ken-Sue Tan , Paul Daniel Wolf , Long Van Pham , Russel A. Martin
发明人： James D. Lyle , Gyudong Kim , Min-Kyu Kim , Ken-Sue Tan , Paul Daniel Wolf , Long Van Pham , Russel A. Martin
IPC分类号： H04J3/06
CPC分类号： H04L7/0008 , G06F3/14 , G09G5/006 , G09G5/008 , G09G2370/045 , G09G2370/047 , H03L7/1974 , H04J3/0632 , H04L25/05 , H04N21/4305 , H04N21/435
摘要： A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver and auxiliary data are transmitted from the receiver to the transmitter (or from the transmitter to the receiver and also from receiver to the transmitter), a transmitter or receiver for use in such a system, and methods for sending auxiliary data and video data over such a link, synchronizing such auxiliary data with such video data, and generating clocks having frequency closely matching the rate at which the auxiliary data are transmitted. Typically, the auxiliary data include one or more streams of audio data. In some embodiments the transmitter transmits a video clock to the receiver over a video clock channel, at least one of the transmitter and receiver transmits at least one stream of auxiliary data to the other one of the transmitter and the receiver, and at least one of the transmitter and the receiver transmits over the video clock channel at least one auxiliary clock for the auxiliary data.
摘要翻译：包括发射机，接收机和类似TMDS的链路的通信系统，其中视频数据和辅助数据从发射机发射到接收机，或者通过链路从发射机到接收机传输视频数据，辅助数据从接收机发送到发射机（或从发射机到接收机，也可以从接收机发送到发射机），用于这种系统的发射机或接收机以及用于在这种系统中发送辅助数据和视频数据的方法链接，使这样的辅助数据与这样的视频数据同步，并产生具有与发送辅助数据的速率非常相似的频率的时钟。通常，辅助数据包括一个或多个音频数据流。在一些实施例中，发射机通过视频时钟信道向接收机发送视频时钟，发射机和接收机中的至少一个将至少一个辅助数据流发射到发射机和接收机中的另一个，以及至少一个发射机和接收机通过视频时钟信道发送辅助数据的至少一个辅助时钟。

4. 发明授权

US07231009B2 Data synchronization across an asynchronous boundary using, for example, multi-phase clocks 有权
标题翻译：使用例如多相时钟的跨异步边界的数据同步
公开(公告)号：US07231009B2
公开(公告)日：2007-06-12
申请号：US10371220
申请日：2003-02-19
申请人： Gyudong Kim , Min-Kyu Kim
发明人： Gyudong Kim , Min-Kyu Kim
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , H04L7/0008
摘要： Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.
摘要翻译：通过使用时钟信号来确定外部时钟信号和第一内部采样时钟信号之间的相位差是否小于预先选择的值来获得关于外部时钟信号的相位的附加信息。如果系统确定相位差小于预先选择的值，则一个实施例用具有与第一内部采样时钟信号选择的相位关系的第二内部采样时钟信号对入局数据进行采样，例如1/2的时钟周期不相位通过在外部时钟的有效边沿和内部采样时钟的有效边沿之间保持足够的相位差，该实施例提供了足够的建立/保持余量以避免子系统跨越异步边界接收数据的亚稳态或其他问题。

5. 发明授权

US09015509B2 Mechanism for low power standby mode control circuit 有权
标题翻译：低功耗待机模式控制电路机制
公开(公告)号：US09015509B2
公开(公告)日：2015-04-21
申请号：US13362930
申请日：2012-01-31
申请人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
发明人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3246 , G06F1/3293 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
摘要翻译：本发明的实施例通常涉及低功率待机模式控制电路。装置的实施例包括处理器，用于与第二装置的连接的接口和操作电路，其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。该设备还包括备用模式控制电路，待机控制电路使用待机电源进行操作，其中待机模式控制电路将检测来自第二设备的激励信号，并且响应于激励信号，备用控制电路为为了向处理器发信号，处理器启用操作电路的一个或多个电源连接。

6. 发明申请

US20120204048A1 MECHANISM FOR LOW POWER STANDBY MODE CONTROL CIRCUIT 有权
标题翻译：低功耗待机模式控制电路的机理
公开(公告)号：US20120204048A1
公开(公告)日：2012-08-09
申请号：US13362930
申请日：2012-01-31
申请人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
发明人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3246 , G06F1/3293 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
摘要翻译：本发明的实施例通常涉及低功率待机模式控制电路。装置的实施例包括处理器，用于与第二装置的连接的接口和操作电路，其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。该设备还包括备用模式控制电路，待机控制电路使用待机电源进行操作，其中待机模式控制电路将检测来自第二设备的激励信号，并且响应于激励信号，备用控制电路为为了向处理器发信号，处理器启用操作电路的一个或多个电源连接。

7. 发明授权

US07599316B2 Bi-directional bridge circuit having high common mode rejection and high input sensitivity 有权
标题翻译：具有高共模抑制和高输入灵敏度的双向电桥电路
公开(公告)号：US07599316B2
公开(公告)日：2009-10-06
申请号：US11441669
申请日：2006-05-25
申请人： Gyudong Kim , Min-Kyu Kim
发明人： Gyudong Kim , Min-Kyu Kim
IPC分类号： H04B1/52 , H04B3/20
CPC分类号： H04B3/30 , H04L25/0276 , H04L25/085
摘要： A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.
摘要翻译：提供了将发射器和接收器或收发器连接到传输线的双向通信接口。在一个实施例中，双向接口使用两个单独的差分放大器产生正极性和负极性数据信号，差分放大器从差分链路的每一侧接收到传输线和发射器的差分信号对。双向接口通过响应于来自每个差分放大器的输出共模反馈电压产生的偏置信号来控制每个单独的差分放大器中的共模抑制。输出放大器组合正极性和负极性数据信号，形成单端输出逻辑信号。输出逻辑信号表示在传输线上接收的数据，并提供给接收机。

8. 发明授权

US07103013B1 Bidirectional bridge circuit having high common mode rejection and high input sensitivity 有权
标题翻译：具有高共模抑制和高输入灵敏度的双向电桥电路
公开(公告)号：US07103013B1
公开(公告)日：2006-09-05
申请号：US09989580
申请日：2001-11-20
申请人： Gyudong Kim , Min-Kyu Kim
发明人： Gyudong Kim , Min-Kyu Kim
IPC分类号： H04B1/52
CPC分类号： H04B3/30 , H04L25/0276 , H04L25/085
摘要： A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.
摘要翻译：提供了将发射器和接收器或收发器连接到传输线的双向通信接口。在一个实施例中，双向接口使用两个单独的差分放大器产生正极性和负极性数据信号，差分放大器从差分链路的每一侧接收到传输线和发射器的差分信号对。双向接口通过响应于来自每个差分放大器的输出共模反馈电压产生的偏置信号来控制每个单独的差分放大器中的共模抑制。输出放大器组合正极性和负极性数据信号，形成单端输出逻辑信号。输出逻辑信号表示在传输线上接收的数据，并提供给接收机。

9. 发明授权

US07062004B1 Method and apparatus for adaptive control of PLL loop bandwidth 有权
标题翻译：用于PLL环路带宽自适应控制的方法和装置
公开(公告)号：US07062004B1
公开(公告)日：2006-06-13
申请号：US09905511
申请日：2001-07-13
申请人： Gyudong Kim , Min-Kyu Kim , Ook Kim , Eric A. Lee , Bruce Kim
发明人： Gyudong Kim , Min-Kyu Kim , Ook Kim , Eric A. Lee , Bruce Kim
IPC分类号： H04L7/00
CPC分类号： H03L7/093 , H03L7/0898 , H04L7/0337
摘要： A scheme for reducing jitter in high-speed digital communication by adaptively controlling the loop bandwidth of a receiver PLL to reduce the relative jitter between the recovered data and clock. The scheme uses phase pointer activity to represent the relative jitter. The phase pointer activity is measured and used to control the receiver PLL loop bandwidth. The receiver PLL loop bandwidth is repeatedly incremented or decremented by a step size based on the comparison between a newly measured activity value and the old activity value, until the phase pointer activity reaches a minimum. Because the PLL performance requirement of the transmitter can be relaxed, compatibility with legacy transmitters and multi-vendor transmitters is enhanced. Because tight control of fabrication process parameters of PLLs may be relaxed, the fabrication yield may also be improved.
摘要翻译：通过自适应地控制接收机PLL的环路带宽以减少恢复的数据和时钟之间的相对抖动来减少高速数字通信中的抖动的方案。该方案使用相位指针活动来表示相对抖动。测量相位指针活动并用于控制接收机PLL环路带宽。基于新测量的活动值和旧活动值之间的比较，接收机PLL环路带宽被重复地增加或减小步长，直到相位指针活动达到最小值。因为发射机的PLL性能要求可以放宽，与传统发射机和多厂商发射机的兼容性得到增强。由于PLL的制造工艺参数的紧密控制可以被放宽，所以也可以提高制造成品率。

10. 发明申请

US20090323830A1 CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE 有权
标题翻译：电流模式电路来调制共模电压
公开(公告)号：US20090323830A1
公开(公告)日：2009-12-31
申请号：US12555300
申请日：2009-09-08
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H04B3/00 , H03K19/094 , H03K19/0175
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

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