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1. 发明授权

US08484387B2 Detection of cable connections for electronic devices 有权
标题翻译：检测电子设备的电缆连接
公开(公告)号：US08484387B2
公开(公告)日：2013-07-09
申请号：US13172745
申请日：2011-06-29
申请人： Gyudong Kim , Chandlee Harrell , Shrikant Ranade , Alexander Pevsakhovich
发明人： Gyudong Kim , Chandlee Harrell , Shrikant Ranade , Alexander Pevsakhovich
IPC分类号： G06F3/00 , G06F13/00 , G06F13/36
CPC分类号： G06F13/4072
摘要： Embodiments of the invention are generally directed to detection of cable connections for electronic devices. An embodiment of an apparatus includes a port for the connection of a cable, the port being compatible with a first protocol and a second protocol, the port including multiple pins including a first pin for a first line and a second pin for a second line. The apparatus further includes a processor to determine a type of source device connected to the cable, where determination of the type of source device includes the apparatus detecting a low signal on the first line and a high signal on the second line, and, upon detecting the low signal on first line and the high signal on the second line, the apparatus initiates a discovery sequence, the discovery sequence including transmitting a signal sequence on the second line and attempting to receive the signal sequence on the second line. If the signal sequence is successfully received on the second line, the apparatus determines that a source device compatible with the first protocol is connected to the cable.
摘要翻译：本发明的实施例一般涉及电子设备的电缆连接的检测。装置的实施例包括用于连接电缆的端口，该端口与第一协议和第二协议兼容，该端口包括多个引脚，包括用于第一线路的第一引脚和用于第二线路的第二引脚。该装置还包括处理器，用于确定连接到电缆的源设备的类型，其中源设备的类型的确定包括检测第一线路上的低信号的设备和在第二线路上的高信号，并且在检测到第一行上的低信号和第二行上的高信号，装置启动发现序列，发现序列包括在第二行上发送信号序列并尝试在第二行上接收信号序列。如果在第二行上成功接收到信号序列，则装置确定与第一协议兼容的源设备连接到电缆。

2. 发明申请

US20120182473A1 MECHANISM FOR CLOCK RECOVERY FOR STREAMING CONTENT BEING COMMUNICATED OVER A PACKETIZED COMMUNICATION NETWORK 审中-公开
标题翻译：用于通过封装通信网络传播的内容流的时钟恢复机制
公开(公告)号：US20120182473A1
公开(公告)日：2012-07-19
申请号：US13339339
申请日：2011-12-28
申请人： Gyudong Kim , Hoon Choi , Richard J. Wilcox , Chandlee Harrell
发明人： Gyudong Kim , Hoon Choi , Richard J. Wilcox , Chandlee Harrell
IPC分类号： H04N5/06 , H04L7/00
摘要： A mechanism for facilitating clock recovery for streaming content over a packetized network is described. A method of embodiments includes receiving an estimated data stream at a first device. The estimated data stream may include estimated data format information relating to a data stream expected to be received at the first device. The method may further include performing, at the first device, clock regeneration of the estimated data stream based on the estimated data format information. The clock regeneration may include performing clock recovery of the estimated data stream.
摘要翻译：描述了一种用于促进在分组化网络上流式传输内容的时钟恢复的机制。实施例的方法包括在第一设备处接收估计的数据流。估计数据流可以包括与预期在第一设备处接收的数据流有关的估计数据格式信息。该方法还可以包括在第一设备处，基于估计的数据格式信息执行估计数据流的时钟再生。时钟再生可以包括执行估计数据流的时钟恢复。

3. 发明授权

US07502411B2 Method and circuit for adaptive equalization of multiple signals in response to a control signal generated from one of the equalized signals 有权
标题翻译：响应于从一个均衡信号产生的控制信号，多个信号的自适应均衡的方法和电路
公开(公告)号：US07502411B2
公开(公告)日：2009-03-10
申请号：US10794015
申请日：2004-03-05
申请人： Ook Kim , Gyudong Kim
发明人： Ook Kim , Gyudong Kim
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03019
摘要： In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal. In other embodiments, the invention is an adaptive equalization circuit including an equalization filter and circuitry for generating a control signal for the filter in response to a signal indicative of a predetermined fixed pattern, a receiver including an adaptive equalization circuit, a system including such a receiver, and a method for adaptive equalization of signals received over a multi-channel serial link.
摘要翻译：在优选实施例中，自适应均衡电路包括至少两个均衡滤波器（每个用于均衡通过多通道串行链路传输的信号）和用于产生用于所有滤波器的均衡控制信号的控制电路。控制电路响应于由滤波器之一产生的均衡信号而产生控制信号，并将控制信号置为全部滤波器。优选地，一个滤波器响应于固定模式信号（例如，时钟信号）产生均衡的固定模式信号，每个其他滤波器均衡数据信号，并且控制电路响应于均衡的固定模式信号而产生控制信号。在其他实施例中，本发明是一种自适应均衡电路，包括均衡滤波器和用于响应于指示预定固定模式的信号产生用于滤波器的控制信号的电路，包括自适应均衡电路的接收机，接收机和用于通过多声道串行链路接收的信号的自适应均衡的方法。

4. 发明授权

US07295578B1 Method and apparatus for synchronizing auxiliary data and video data transmitted over a TMDS-like link 有权
标题翻译：用于同步辅助数据和通过类似TMDS的链路传输的视频数据的方法和装置
公开(公告)号：US07295578B1
公开(公告)日：2007-11-13
申请号：US09954291
申请日：2001-09-12
申请人： James D. Lyle , Gyudong Kim , Min-Kyu Kim , Ken-Sue Tan , Paul Daniel Wolf , Long Van Pham , Russel A. Martin
发明人： James D. Lyle , Gyudong Kim , Min-Kyu Kim , Ken-Sue Tan , Paul Daniel Wolf , Long Van Pham , Russel A. Martin
IPC分类号： H04J3/06
CPC分类号： H04L7/0008 , G06F3/14 , G09G5/006 , G09G5/008 , G09G2370/045 , G09G2370/047 , H03L7/1974 , H04J3/0632 , H04L25/05 , H04N21/4305 , H04N21/435
摘要： A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver and auxiliary data are transmitted from the receiver to the transmitter (or from the transmitter to the receiver and also from receiver to the transmitter), a transmitter or receiver for use in such a system, and methods for sending auxiliary data and video data over such a link, synchronizing such auxiliary data with such video data, and generating clocks having frequency closely matching the rate at which the auxiliary data are transmitted. Typically, the auxiliary data include one or more streams of audio data. In some embodiments the transmitter transmits a video clock to the receiver over a video clock channel, at least one of the transmitter and receiver transmits at least one stream of auxiliary data to the other one of the transmitter and the receiver, and at least one of the transmitter and the receiver transmits over the video clock channel at least one auxiliary clock for the auxiliary data.
摘要翻译：包括发射机，接收机和类似TMDS的链路的通信系统，其中视频数据和辅助数据从发射机发射到接收机，或者通过链路从发射机到接收机传输视频数据，辅助数据从接收机发送到发射机（或从发射机到接收机，也可以从接收机发送到发射机），用于这种系统的发射机或接收机以及用于在这种系统中发送辅助数据和视频数据的方法链接，使这样的辅助数据与这样的视频数据同步，并产生具有与发送辅助数据的速率非常相似的频率的时钟。通常，辅助数据包括一个或多个音频数据流。在一些实施例中，发射机通过视频时钟信道向接收机发送视频时钟，发射机和接收机中的至少一个将至少一个辅助数据流发射到发射机和接收机中的另一个，以及至少一个发射机和接收机通过视频时钟信道发送辅助数据的至少一个辅助时钟。

5. 发明授权

US07231009B2 Data synchronization across an asynchronous boundary using, for example, multi-phase clocks 有权
标题翻译：使用例如多相时钟的跨异步边界的数据同步
公开(公告)号：US07231009B2
公开(公告)日：2007-06-12
申请号：US10371220
申请日：2003-02-19
申请人： Gyudong Kim , Min-Kyu Kim
发明人： Gyudong Kim , Min-Kyu Kim
IPC分类号： H04L7/00
CPC分类号： H04L7/0012 , H04L7/0008
摘要： Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.
摘要翻译：通过使用时钟信号来确定外部时钟信号和第一内部采样时钟信号之间的相位差是否小于预先选择的值来获得关于外部时钟信号的相位的附加信息。如果系统确定相位差小于预先选择的值，则一个实施例用具有与第一内部采样时钟信号选择的相位关系的第二内部采样时钟信号对入局数据进行采样，例如1/2的时钟周期不相位通过在外部时钟的有效边沿和内部采样时钟的有效边沿之间保持足够的相位差，该实施例提供了足够的建立/保持余量以避免子系统跨越异步边界接收数据的亚稳态或其他问题。

6. 发明申请

US20070098112A1 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US20070098112A1
公开(公告)日：2007-05-03
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04L27/04 , H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

7. 发明申请

US20050182876A1 Cable with circuitry for asserting stored cable data or other information to an external device or user 有权
标题翻译：电缆，用于将存储的电缆数据或其他信息断言给外部设备或用户
公开(公告)号：US20050182876A1
公开(公告)日：2005-08-18
申请号：US10781405
申请日：2004-02-18
申请人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Kim , Gijung Ahn , Seung Hwang
发明人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Kim , Gijung Ahn , Seung Hwang
IPC分类号： G06F13/00 , G06F13/38
CPC分类号： G06F13/385
摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
摘要翻译：包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体（例如，用于传输到外部设备）。本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对歪斜等信息。电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

8. 发明授权

US6157360A System and method for driving columns of an active matrix display 失效
标题翻译：用于驱动有源矩阵显示器的列的系统和方法
公开(公告)号：US6157360A
公开(公告)日：2000-12-05
申请号：US815486
申请日：1997-03-11
申请人： Deog-Kyoon Jeong , Gyudong Kim , Ho Young Song , David D. Lee
发明人： Deog-Kyoon Jeong , Gyudong Kim , Ho Young Song , David D. Lee
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/027 , G09G3/3696
摘要： Described is a system and method for driving columns of an active matrix display using a resistor-string digital-to-analog converter (DAC). The description includes an auto-stop buffer circuit that drives an analog data voltage in two steps--the first step being active buffering by a "dead-zone amplifier" before the output reaches a certain level and the second step being acting as a passive conduit after the output reaches the certain level. The dead-zone amplifier inherently turns itself off when the analog voltage reaches the certain level. Also described are various column driver architectures in which buffers are placed in various ways in a column driver in between the resistor-string DAC and the column decoders in order to minimize the number of required buffers.
摘要翻译：描述了一种使用电阻串数模转换器（DAC）驱动有源矩阵显示器列的系统和方法。该描述包括以两步驱动模拟数据电压的自动停止缓冲电路 - 第一步是在输出达到一定水平之前由“死区放大器”进行主动缓冲，第二步用作无源导管输出达到一定水平后。当模拟电压达到一定水平时，死区放大器本身就会自动关闭。还描述了各种列驱动器架构，其中缓冲器以各种方式放置在电阻器串DAC和列解码器之间的列驱动器中，以便使所需缓冲器的数量最小化。

9. 发明授权

US09143507B2 Method, apparatus, and system for pre-authentication and processing of data streams 有权
标题翻译：用于预认证和处理数据流的方法，装置和系统
公开(公告)号：US09143507B2
公开(公告)日：2015-09-22
申请号：US12392000
申请日：2009-02-24
申请人： Hoon Choi , Gyudong Kim , Ook Kim , Alexander Peysakhovich , Michael Schumacher , Daeyun Shim
发明人： Hoon Choi , Gyudong Kim , Ook Kim , James D. Lyle , Alexander Peysakhovich , Michael Schumacher , Daeyun Shim
IPC分类号： H04L29/06
CPC分类号： H04L63/0876 , G09G5/006 , G09G2370/12 , G11B20/00086 , G11B20/00463 , H04N5/4401 , H04N5/913 , H04N7/1675 , H04N21/2541 , H04N21/4122 , H04N21/4367 , H04N21/4408 , H04N21/835
摘要： A method, apparatus and system for pre-authenticating ports is disclosed. In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so the pre-authenticated inactive ports can subsequently replace the active port if a port switch is performed.
摘要翻译：公开了一种用于预认证端口的方法，装置和系统。在一个实施例中，识别促进传输设备和接收设备之间的媒体内容通信的活动端口，而活动端口与第一高清内容保护（HDCP）引擎相关联。然后，识别处于空闲模式的非活动端口作为活动端口的备份端口，而非活动端口与第二HDCP引擎相关联。执行每个非活动端口的预认证，使得如果执行端口交换机，则经过认证的非活动端口可以随后替换活动端口。

10. 发明授权

US09015509B2 Mechanism for low power standby mode control circuit 有权
标题翻译：低功耗待机模式控制电路机制
公开(公告)号：US09015509B2
公开(公告)日：2015-04-21
申请号：US13362930
申请日：2012-01-31
申请人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
发明人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3246 , G06F1/3293 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
摘要翻译：本发明的实施例通常涉及低功率待机模式控制电路。装置的实施例包括处理器，用于与第二装置的连接的接口和操作电路，其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。该设备还包括备用模式控制电路，待机控制电路使用待机电源进行操作，其中待机模式控制电路将检测来自第二设备的激励信号，并且响应于激励信号，备用控制电路为为了向处理器发信号，处理器启用操作电路的一个或多个电源连接。

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