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1. 发明授权

US08362642B2 Optimized power supply for an electronic system 有权
标题翻译：优化电子系统的电源
公开(公告)号：US08362642B2
公开(公告)日：2013-01-29
申请号：US12528566
申请日：2008-02-28
申请人： Jared LeVan Zerbe , Jaeha Kim , Yohan U. Frans , Huy M. Nguyen
发明人： Jared LeVan Zerbe , Jaeha Kim , Yohan U. Frans , Huy M. Nguyen
IPC分类号： H02J1/10
CPC分类号： G05F1/10 , G06F1/26 , Y10T307/406 , Y10T307/50
摘要： A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.
摘要翻译：根据与有线通信链路相关联的性能度量来调整与有线通信链路耦合的电子设备的电压供应的方法。基于性能度量产生电压调整信号。然后，电压调整信号用于更新对电子设备的电压供应。

2. 发明授权

US08279976B2 Signaling with superimposed differential-mode and common-mode signals 有权
标题翻译：信号叠加差分模式和共模信号
公开(公告)号：US08279976B2
公开(公告)日：2012-10-02
申请号：US12739938
申请日：2008-10-28
申请人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H03K9/00
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。提取的数据信号具有与提取的时钟信号的频率相对应的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

3. 发明授权

US08159274B2 Signaling with superimposed clock and data signals 有权
标题翻译：信号叠加时钟和数据信号
公开(公告)号：US08159274B2
公开(公告)日：2012-04-17
申请号：US12739936
申请日：2008-10-28
申请人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H04L7/0008 , H04L7/065 , H04L25/0276 , H04L25/14
摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
摘要翻译：数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。第一速率是第二速率的倍数，其中倍数大于1。数据传输电路还包括与符号时钟同步的数据驱动器。数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。数据信号和时钟信号同时被驱动到一个或多个传输线上。

4. 发明申请

US20100102868A1 Hardware and Method to Test Phase Linearity of Phase Synthesizer 失效
标题翻译：测试相位合成器的相位线性度的硬件和方法
公开(公告)号：US20100102868A1
公开(公告)日：2010-04-29
申请号：US12531830
申请日：2008-03-14
申请人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
发明人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
IPC分类号： G06F1/04
CPC分类号： H03M1/109 , G01R31/31725 , G01R31/31726 , G01R31/31727 , H03M1/66
摘要： A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.
摘要翻译：用于测试相位合成器的相位线性度的电路，其合成具有相应于输入到相位合成器的数字相位值的相位的输出时钟。数字计数器向相位合成器提供数字相位值。数字计数器接收与输入时钟同步的计数器时钟。数字相位值由数字计数器步进，从而移位输出时钟的频率。对相位合成器的相位线性度分析输出时钟，以产生相位线性分析输出。

5. 发明申请

US20100085123A1 INJECTION-LOCKED CLOCK MULTIPLIER 审中-公开
标题翻译：注射锁定时间累加器
公开(公告)号：US20100085123A1
公开(公告)日：2010-04-08
申请号：US12577027
申请日：2009-10-09
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Jaeha Kim
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Jaeha Kim
IPC分类号： H03L7/24
CPC分类号： H03L7/083 , H03L7/099 , H03L7/18
摘要： Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, on injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one.
摘要翻译：描述时钟电路的实施例。该时钟电路包括振荡器，其包括具有谐振频率的谐振电路，该谐振电路输出具有第一频率的第一时钟信号。此外，数字控制器耦合到振荡器。该数字控制器在时钟电路的第一操作模式期间修改振荡器的谐振频率，并且在时钟电路的第二操作模式期间中止修改。另外，注入电路耦合到振荡器。该注入电路向振荡器提供具有第二频率的第二时钟信号。注意，第二时钟信号注入锁定第一时钟信号的相位和/或第一频率。还要注意，第一频率与第二频率的比率大于或等于1。

6. 发明授权

US08929496B2 Receiver with enhanced clock and data recovery 有权
标题翻译：接收机具有增强的时钟和数据恢复功能
公开(公告)号：US08929496B2
公开(公告)日：2015-01-06
申请号：US12812720
申请日：2009-01-30
申请人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
发明人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
IPC分类号： H04L7/00 , H04L7/033 , H04L25/06 , H04L25/03 , H04L27/00
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
摘要翻译：接收机设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。在示例实施例中，设备实现第一相位调节控制回路，例如，一个爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换以便在边缘采样器的最优边缘时间调整采样的采样器。该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。

7. 发明授权

US08422590B2 Apparatus and methods for differential signal receiving 有权
标题翻译：差分信号接收的装置和方法
公开(公告)号：US08422590B2
公开(公告)日：2013-04-16
申请号：US12746018
申请日：2008-10-29
申请人： Brian S. Leibowitz , Jaeha Kim , Hae-Chang Lee
发明人： Brian S. Leibowitz , Jaeha Kim , Hae-Chang Lee
IPC分类号： H04L27/00
CPC分类号： H04L7/0338 , H03K5/133 , H04L7/0008
摘要： A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by—multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.
摘要翻译：差分信号接收机106实现对对偏斜补偿，以改善差分信道上的数据传输。在一个实施例中，接收机以不同的相位实现采样多个时钟，使得差分信道的信号可以单独地或单独地进行时间调整以解决它们之间的偏斜，使得它们可以被差分地比较用于数据分辨率。在一个实施例中，正采样器和负采样器由不同的时钟信号控制，以允许在不同时间对表示差分信道上的数据位的正和负信号进行采样和保持。然后差分判决电路可以使用不同时钟信号中的后一个来差分地解析数据。用于产生偏移时钟的定时发生电路可以包括偏斜检测器，其允许根据与差分信道的信号相关联的偏斜动态调整不同的时钟信号。

8. 发明授权

US08155174B2 Hardware and method to test phase linearity of phase synthesizer 失效
标题翻译：测试相位合成器相位线性的硬件和方法
公开(公告)号：US08155174B2
公开(公告)日：2012-04-10
申请号：US12531830
申请日：2008-03-14
申请人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
发明人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
IPC分类号： H04B3/46
CPC分类号： H03M1/109 , G01R31/31725 , G01R31/31726 , G01R31/31727 , H03M1/66
摘要： A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.
摘要翻译：用于测试相位合成器的相位线性度的电路，其合成具有相应于输入到相位合成器的数字相位值的相位的输出时钟。数字计数器向相位合成器提供数字相位值。数字计数器接收与输入时钟同步的计数器时钟。数字相位值由数字计数器步进，从而移位输出时钟的频率。对相位合成器的相位线性度分析输出时钟，以产生相位线性分析输出。

9. 发明申请

US20110228616A1 Clock Generator Circuits with Non-Volatile Memory for Storing and/or Feedback-Controlling Phase and Frequency 有权
标题翻译：具有用于存储和/或反馈控制相位和频率的非易失性存储器的时钟发生器电路
公开(公告)号：US20110228616A1
公开(公告)日：2011-09-22
申请号：US12674598
申请日：2008-08-22
申请人： Jaeha Kim , Brent Haukness
发明人： Jaeha Kim , Brent Haukness
IPC分类号： G11C8/18 , G11C7/00
CPC分类号： H03L7/187 , H03L7/0812 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10 , H03L2207/08
摘要： A clock-signal generator (e.g. a PLL or a DLL) uses non-volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, NVM 105 stores the control voltage during periods of inactivity, such as when the signal generator is powered down or in a standby mode. Non-volatile memory stores control voltages during operation in other embodiments to relax the area requirements otherwise required for integration capacitors to store phase and frequency information.
摘要翻译：时钟信号发生器（例如PLL或DLL）使用非易失性存储器来存储确定时钟信号发生器的输出相位和/或频率的模拟控制电压。锁定环路需要时间来锁定给定的参考频率。为了将此时间保持在最低限度，NVM105在不活动期间存储控制电压，例如当信号发生器断电或处于待机模式时。非易失性存储器在其他实施例中在操作期间存储控制电压，以放松否则为积分电容器存储相位和频率信息所需的面积要求。

10. 发明申请

US20100289544A1 Receiver With Enhanced Clock And Data Recovery 有权
标题翻译：接收机具有增强的时钟和数据恢复功能
公开(公告)号：US20100289544A1
公开(公告)日：2010-11-18
申请号：US12812720
申请日：2009-01-30
申请人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
发明人： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
IPC分类号： H03L7/06
CPC分类号： H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
摘要： A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
摘要翻译：接收机设备利用基于边缘的时钟和数据恢复来实现增强的数据接收，例如使用闪存模数转换器架构。在示例实施例中，设备实现第一相位调节控制回路，例如，一个爆炸相位检测器，其通过调整边沿时钟的相位来检测数据转换以便在边缘采样器的最优边缘时间调整采样的采样器。该循环可以通过调整诸如闪存ADC的数据采样器的数据时钟的相位来进一步调整接收数据间隔中的采样以实现最佳数据接收。该装置还可以实现具有例如波特率相位检测器的第二相位调整控制回路，波形率相位检测器检测数据间隔以便在数据采样器的最佳数据时间进一步调整采样。

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