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1. 发明申请

US20090323830A1 CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE 有权
标题翻译：电流模式电路来调制共模电压
公开(公告)号：US20090323830A1
公开(公告)日：2009-12-31
申请号：US12555300
申请日：2009-09-08
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H04B3/00 , H03K19/094 , H03K19/0175
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

2. 发明授权

US07589559B2 Current mode circuitry to modulate a common mode voltage 有权
标题翻译：用于调制共模电压的电流模式电路
公开(公告)号：US07589559B2
公开(公告)日：2009-09-15
申请号：US11643388
申请日：2006-12-20
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H03K19/0175
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

3. 发明申请

US20080169838A1 Current mode circuitry to modulate a common mode voltage 有权
标题翻译：用于调制共模电压的电流模式电路
公开(公告)号：US20080169838A1
公开(公告)日：2008-07-17
申请号：US11643388
申请日：2006-12-20
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H01P5/00
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

4. 发明授权

US07872498B2 Current mode circuitry to modulate a common mode voltage 有权
标题翻译：用于调制共模电压的电流模式电路
公开(公告)号：US07872498B2
公开(公告)日：2011-01-18
申请号：US12555300
申请日：2009-09-08
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H03K19/0175
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

5. 发明授权

US09015509B2 Mechanism for low power standby mode control circuit 有权
标题翻译：低功耗待机模式控制电路机制
公开(公告)号：US09015509B2
公开(公告)日：2015-04-21
申请号：US13362930
申请日：2012-01-31
申请人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
发明人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3246 , G06F1/3293 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
摘要翻译：本发明的实施例通常涉及低功率待机模式控制电路。装置的实施例包括处理器，用于与第二装置的连接的接口和操作电路，其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。该设备还包括备用模式控制电路，待机控制电路使用待机电源进行操作，其中待机模式控制电路将检测来自第二设备的激励信号，并且响应于激励信号，备用控制电路为为了向处理器发信号，处理器启用操作电路的一个或多个电源连接。

6. 发明申请

US20120204048A1 MECHANISM FOR LOW POWER STANDBY MODE CONTROL CIRCUIT 有权
标题翻译：低功耗待机模式控制电路的机理
公开(公告)号：US20120204048A1
公开(公告)日：2012-08-09
申请号：US13362930
申请日：2012-01-31
申请人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
发明人： Gyudong Kim , Eungu Kim , Min-Kyu Kim , Daeyun Shim , Ravi Sharma , Myounghwan Kim , Jaeryon Lee
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3246 , G06F1/3293 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.
摘要翻译：本发明的实施例通常涉及低功率待机模式控制电路。装置的实施例包括处理器，用于与第二装置的连接的接口和操作电路，其中处理器在待机模式下禁用与操作电路的一个或多个电源连接。该设备还包括备用模式控制电路，待机控制电路使用待机电源进行操作，其中待机模式控制电路将检测来自第二设备的激励信号，并且响应于激励信号，备用控制电路为为了向处理器发信号，处理器启用操作电路的一个或多个电源连接。

7. 发明授权

US06897793B1 Method and apparatus for run length limited TMDS-like encoding of data 有权
标题翻译：运行长度限制的方法和装置TMDS类似的数据编码
公开(公告)号：US06897793B1
公开(公告)日：2005-05-24
申请号：US10835301
申请日：2004-04-29
申请人： Gyudong Kim , Hoon Choi , Min-Kyu Kim , Daeyun Shim
发明人： Gyudong Kim , Hoon Choi , Min-Kyu Kim , Daeyun Shim
IPC分类号： H03M5/14 , H03M7/00
CPC分类号： H03M5/145
摘要： A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments, the RLL code word sequence includes both transition-maximized code words and transition-minimized code words. Other aspects of the invention are circuitry and methods for TMDS-like encoding of data for transmission as an RLL code word sequence.
摘要翻译：一种串行数据传输系统，其中发射机根据TMDS编码算法对数据进行编码，并通过串行链路将TMDS类编码数据发送到接收机。编码数据作为游程长度限制（“RLL”）码字序列发送，包括转换最小化码字。在一些实施例中，RLL码字序列仅包括最小字，包括直流平衡最小字和直流不平衡最小字。在其他实施例中，RLL码字序列包括转换最大化码字和转换最小码字。本发明的其他方面是用于作为RLL码字序列传输的数据的TMDS类编码的电路和方法。

8. 发明授权

US07158593B2 Combining a clock signal and a data signal 有权
标题翻译：组合时钟信号和数据信号
公开(公告)号：US07158593B2
公开(公告)日：2007-01-02
申请号：US10099533
申请日：2002-03-15
申请人： Gyudong Kim , Ook Kim , Min-Kyu Kim , Bruce Kim , Seung Ho Hwang
发明人： Gyudong Kim , Ook Kim , Min-Kyu Kim , Bruce Kim , Seung Ho Hwang
IPC分类号： H04L7/00
CPC分类号： H04L25/4902 , G09G5/006 , H04L5/06 , H04L7/0008 , H04L7/0054 , H04L7/027
摘要： A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.
摘要翻译：公开了一种在包括至少一个数据信道和单独的时钟信道的系统中发送数据的方法。该方法包括将要在时钟信道上发送的时钟信号与数据信号组合以产生组合的时钟和数据信号。在一个实施例中，数据信号已经使用使数据信号的能谱偏离时钟信号的能谱的编码方案从数据字生成。在另一个实施例中，时钟信号具有多个脉冲，每个脉冲具有前沿和后沿，并且数据信号通过移动多个脉冲的至少一个边缘（即，前面或背面或两者）被调制到时钟信号上脉冲，从而创建一个组合的时钟和数据信号。

9. 发明授权

US06463092B1 System and method for sending and receiving data signals over a clock signal line 有权
标题翻译：用于通过时钟信号线发送和接收数据信号的系统和方法
公开(公告)号：US06463092B1
公开(公告)日：2002-10-08
申请号：US09393235
申请日：1999-09-09
申请人： Gyudong Kim , Min-Kyu Kim , Seung Ho Hwang
发明人： Gyudong Kim , Min-Kyu Kim , Seung Ho Hwang
IPC分类号： H04B138
CPC分类号： G09G5/006 , G09G5/008 , G09G2370/04 , H04L7/0008 , H04L25/4902
摘要： The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.
摘要翻译：该系统优选地包括在同一传输线上发送时钟和数据信号的唯一发射机。接收机使用相同的传输线将数据信号发送回发射机。发射机包括时钟发生器，解码器和线路接口。时钟发生器产生包括可变位置下降沿的时钟信号。下降沿位置被接收器解码以从时钟信号中提取数据。接收机包括时钟再生器，数据解码器和返回通道编码器。时钟再发生器监视传输线，接收信号，对它们进行滤波，并在接收机上根据传输线上的信号产生时钟信号。返回通道编码器产生信号并在传输线上断言它们。该信号被断言或叠加在发射机提供的时钟和数据信号上。

10. 发明授权

US07295578B1 Method and apparatus for synchronizing auxiliary data and video data transmitted over a TMDS-like link 有权
标题翻译：用于同步辅助数据和通过类似TMDS的链路传输的视频数据的方法和装置
公开(公告)号：US07295578B1
公开(公告)日：2007-11-13
申请号：US09954291
申请日：2001-09-12
申请人： James D. Lyle , Gyudong Kim , Min-Kyu Kim , Ken-Sue Tan , Paul Daniel Wolf , Long Van Pham , Russel A. Martin
发明人： James D. Lyle , Gyudong Kim , Min-Kyu Kim , Ken-Sue Tan , Paul Daniel Wolf , Long Van Pham , Russel A. Martin
IPC分类号： H04J3/06
CPC分类号： H04L7/0008 , G06F3/14 , G09G5/006 , G09G5/008 , G09G2370/045 , G09G2370/047 , H03L7/1974 , H04J3/0632 , H04L25/05 , H04N21/4305 , H04N21/435
摘要： A communication system including a transmitter, a receiver, and a TMDS-like link, in which video data and auxiliary data are transmitted from the transmitter to the receiver, or in which video data are transmitted over the link from the transmitter to the receiver and auxiliary data are transmitted from the receiver to the transmitter (or from the transmitter to the receiver and also from receiver to the transmitter), a transmitter or receiver for use in such a system, and methods for sending auxiliary data and video data over such a link, synchronizing such auxiliary data with such video data, and generating clocks having frequency closely matching the rate at which the auxiliary data are transmitted. Typically, the auxiliary data include one or more streams of audio data. In some embodiments the transmitter transmits a video clock to the receiver over a video clock channel, at least one of the transmitter and receiver transmits at least one stream of auxiliary data to the other one of the transmitter and the receiver, and at least one of the transmitter and the receiver transmits over the video clock channel at least one auxiliary clock for the auxiliary data.
摘要翻译：包括发射机，接收机和类似TMDS的链路的通信系统，其中视频数据和辅助数据从发射机发射到接收机，或者通过链路从发射机到接收机传输视频数据，辅助数据从接收机发送到发射机（或从发射机到接收机，也可以从接收机发送到发射机），用于这种系统的发射机或接收机以及用于在这种系统中发送辅助数据和视频数据的方法链接，使这样的辅助数据与这样的视频数据同步，并产生具有与发送辅助数据的速率非常相似的频率的时钟。通常，辅助数据包括一个或多个音频数据流。在一些实施例中，发射机通过视频时钟信道向接收机发送视频时钟，发射机和接收机中的至少一个将至少一个辅助数据流发射到发射机和接收机中的另一个，以及至少一个发射机和接收机通过视频时钟信道发送辅助数据的至少一个辅助时钟。

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