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1. 发明授权

US07627044B2 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US07627044B2
公开(公告)日：2009-12-01
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

2. 发明申请

US20070098112A1 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US20070098112A1
公开(公告)日：2007-05-03
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04L27/04 , H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

3. 发明授权

US07102446B1 Phase lock loop with coarse control loop having frequency lock detector and device including same 有权
标题翻译：具有粗调控制回路的锁相环具有频率锁定检测器和包括其的装置
公开(公告)号：US07102446B1
公开(公告)日：2006-09-05
申请号：US11056995
申请日：2005-02-11
申请人： Hyung-Rok Lee , Moon-Sang Hwang , Sang-Hyun Lee , Bong-Joon Lee , Deog-Kyoon Jeong
发明人： Hyung-Rok Lee , Moon-Sang Hwang , Sang-Hyun Lee , Bong-Joon Lee , Deog-Kyoon Jeong
IPC分类号： H03L7/07 , H03L7/087 , H04B1/40 , H04B1/50
CPC分类号： H03L7/087 , H03K23/507 , H03L7/089 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/10 , H03L2207/06 , H04L7/0337 , Y10S331/02
摘要： A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.
摘要翻译：用于控制采样时钟或其他时钟的锁相环（PLL）以及数据采样电路，收发器或包括这种PLL的其它装置。 PLL包括多范围VCO，用于控制VCO的至少一个精细控制环路和用于通过改变其频率 - 电压特性来控制VCO的粗略控制环路。粗调控制回路包括一个频率锁定检测器和电压范围监控逻辑。通常，当VCO输出时钟频率和参考频率之间的差减小到预定阈值时，频率锁定检测器锁定粗略控制环路的操作，而解锁的粗略控制环路采用电压范围监控逻辑来改变VCO频率当VCO的精细控制电压离开预定范围时的电压特性。其他方面是实现采用不超过三个PLL用于时钟产生的时钟方案的收发器（包括至少两个接收器接口和发射器接口），以及具有包括数字电路和单个时钟产生的多层接收器接口的收发器 PLL（用于产生要由接收器接口的所有层共享的多相时钟的模拟PLL）。每个接收器接口层使用多相时钟在不同的接收信号上执行盲过采样，并且数字电路包括接收过采样数据的多层数字锁相环电路。

4. 发明授权

US07409031B1 Data sampling method and apparatus with alternating edge sampling phase detection for loop characteristic stabilization 有权
标题翻译：具有交替边缘采样相位检测的数据采样方法和装置，用于环路特性稳定
公开(公告)号：US07409031B1
公开(公告)日：2008-08-05
申请号：US10642259
申请日：2003-08-15
申请人： Bong-Joon Lee , Moon-Sang Hwang , Sang-Hyun Lee , Deog-Kyoon Jeong
发明人： Bong-Joon Lee , Moon-Sang Hwang , Sang-Hyun Lee , Deog-Kyoon Jeong
IPC分类号： H03D3/24
CPC分类号： H03L7/10 , H03L7/07 , H03L7/0805 , H03L7/0891 , H03L7/0995 , H03L7/107 , H04L7/0083 , H04L7/0091 , H04L7/033
摘要： A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 μm CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10−12.
摘要翻译：一种用于对具有抖动的数据进行2x过采样的方法和装置。在一些实施例中，本发明是包括交替边缘采样二进制相位检测器的时钟和数据恢复装置，其被配置为稳定各种抖动环境中的环路特性，并且可以以小的硬件开销来实现。实现本发明的收发器可以被实现为使用0.18mum CMOS工艺的CMOS集成电路，收发器芯片能够从消耗串行链路接收的信号中恢复具有高达11.5Gbps的数据速率的数据，同时消耗 1.8V电源不超过540mW，误码率小于10 -12 。

5. 发明申请

US20080247341A1 DIGITAL VIDEO INTERFACE WITH BI-DIRECTIONAL HALF-DUPLEX CLOCK CHANNEL USED AS AUXILIARY DATA CHANNEL 有权
标题翻译：数字视频接口，双向双向双向通道，用作辅助数据通道
公开(公告)号：US20080247341A1
公开(公告)日：2008-10-09
申请号：US11760164
申请日：2007-06-08
申请人： Bong-Joon Lee
发明人： Bong-Joon Lee
IPC分类号： H04L5/22 , H04L5/16
CPC分类号： H04L5/16 , H04L7/0008 , H04N5/775 , H04N7/10 , H04N9/44 , H04N9/64 , H04N11/042
摘要： A digital video interface system and method for communicating digital video data from a source device to a sink device is provided, where the clock channel is used to transmit data as well as clock signals in a bi-directional, half-duplex manner using time division multiplexing. The digital video interface system comprises one or more data channels configured to transmit digital video data from the source device to the sink device in time divisional multiplexing including a plurality of first time slots and second time slots, and a clock channel configured to transmit a clock signal from the source device to the sink device in the first time slots and configured to transmit additional data from the source device to the sink device or from the sink device to the source device in the second time slots.
摘要翻译：提供了一种用于将数字视频数据从源设备传送到宿设备的数字视频接口系统和方法，其中时钟信道用于以双向，半双工方式使用时分传输数据以及时钟信号复用。数字视频接口系统包括一个或多个数据通道，配置成在包括多个第一时隙和第二时隙的时分复用中将数字视频数据从源设备传输到宿设备，以及时钟信道，被配置为发送时钟在第一时隙中从源设备到宿设备的信号，并且被配置为在第二时隙中从源设备向宿设备或从宿设备传输附加数据到源设备。

6. 发明申请

US20090245345A1 Bi-Directional Digital Interface for Video and Audio (DIVA) 有权
标题翻译：视频和音频双向数字接口（DIVA）
公开(公告)号：US20090245345A1
公开(公告)日：2009-10-01
申请号：US12057051
申请日：2008-03-27
申请人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byong-Woon Kim
发明人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byong-Woon Kim
IPC分类号： H04N11/02
CPC分类号： H04N5/44 , H04N5/765 , H04N5/85 , H04N21/4305 , H04N21/43632 , H04N21/43635
摘要： A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.
摘要翻译：一种通信系统，包括第一节点，第二节点，第一节点和第二节点之间的串行通信链路，用于经由链路的一个或多个视频信道从第一节点向第二节点发送数字视频数据。所述通信系统还包括在所述第一节点和所述第二节点之间的混合链路，其中所述第一节点和所述第二节点被配置为通过所述混合链路通过混合信道将至少一个数据流发送到另一个。在通信系统中，根据视频像素频率对串行通信链路的带宽进行缩放。此外，串行通信链路的初始锁定由通过混合链路传送的时钟信息辅助。

7. 发明授权

US07940809B2 Digital video interface with bi-directional half-duplex clock channel used as auxiliary data channel 有权
标题翻译：数字视频接口采用双向半双工时钟通道作为辅助数据通道
公开(公告)号：US07940809B2
公开(公告)日：2011-05-10
申请号：US11760164
申请日：2007-06-08
申请人： Bong-Joon Lee
发明人： Bong-Joon Lee
IPC分类号： H04J3/12
CPC分类号： H04L5/16 , H04L7/0008 , H04N5/775 , H04N7/10 , H04N9/44 , H04N9/64 , H04N11/042
摘要： A digital video interface system and method for communicating digital video data from a source device to a sink device is provided, where the clock channel is used to transmit data as well as clock signals in a bi-directional, half-duplex manner using time division multiplexing. The digital video interface system comprises one or more data channels configured to transmit digital video data from the source device to the sink device in time divisional multiplexing including a plurality of first time slots and second time slots, and a clock channel configured to transmit a clock signal from the source device to the sink device in the first time slots and configured to transmit additional data from the source device to the sink device or from the sink device to the source device in the second time slots.
摘要翻译：提供了一种用于将数字视频数据从源设备传送到宿设备的数字视频接口系统和方法，其中时钟信道用于以双向，半双工方式使用时分传输数据以及时钟信号复用。数字视频接口系统包括一个或多个数据通道，配置成在包括多个第一时隙和第二时隙的时分复用中将数字视频数据从源设备传输到宿设备，以及时钟信道，被配置为发送时钟在第一时隙中从源设备到宿设备的信号，并且被配置为在第二时隙中从源设备向宿设备或从宿设备传输附加数据到源设备。

8. 发明授权

US09030976B2 Bi-directional digital interface for video and audio (DIVA) 有权
标题翻译：视频和音频双向数字接口（DIVA）
公开(公告)号：US09030976B2
公开(公告)日：2015-05-12
申请号：US12057051
申请日：2008-03-27
申请人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byoung-Woon Kim
发明人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byoung-Woon Kim
IPC分类号： H04B1/52 , H04N5/44 , H04N5/765 , H04N5/85 , H04N21/43 , H04N21/4363
CPC分类号： H04N5/44 , H04N5/765 , H04N5/85 , H04N21/4305 , H04N21/43632 , H04N21/43635
摘要： A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.
摘要翻译：一种通信系统，包括第一节点，第二节点，第一节点和第二节点之间的串行通信链路，用于经由链路的一个或多个视频信道从第一节点向第二节点发送数字视频数据。所述通信系统还包括在所述第一节点和所述第二节点之间的混合链路，其中所述第一节点和所述第二节点被配置为通过所述混合链路通过混合信道将至少一个数据流发送到另一个。在通信系统中，根据视频像素频率对串行通信链路的带宽进行缩放。此外，串行通信链路的初始锁定由通过混合链路传送的时钟信息辅助。

9. 发明授权

US08908576B2 Bi-directional digital interface for video and audio (DIVA) 有权
公开(公告)号：US08908576B2
公开(公告)日：2014-12-09
申请号：US12057051
申请日：2008-03-27
申请人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byoung-Woon Kim
发明人： Dongyun Lee , John Hahn , Bong-Joon Lee , David Lee , Byoung-Woon Kim
IPC分类号： H04B1/52 , H04N5/44 , H04N21/43 , H04N5/765 , H04N5/85 , H04N21/4363
摘要： A communication system, comprising a first node, a second node, a serial communication link between the first node and the second node, configured to transmit digital video data from the first node to the second node over one or more video channels of the link. The communication system further including a hybrid link between the first node and the second node, wherein the first node and the second node are configured to transmit at least one stream of data to the other through a hybrid channel over the hybrid link. In the communication system, the bandwidth of the serial communication link is scaled according to a video pixel frequency. Further, the initial locking of the serial communication link is aided by clock information delivered over the hybrid link.

10. 发明授权

US07916780B2 Adaptive equalizer for use with clock and data recovery circuit of serial communication link 有权
标题翻译：自适应均衡器，用于串行通信链路的时钟和数据恢复电路
公开(公告)号：US07916780B2
公开(公告)日：2011-03-29
申请号：US11865621
申请日：2007-10-01
申请人： Bong-Joon Lee
发明人： Bong-Joon Lee
IPC分类号： H03K5/159
CPC分类号： H04L25/03019 , H04L7/0004 , H04L7/033 , H04L25/03885 , H04L2025/03356 , H04L2025/03598
摘要： An adaptive equalizer system for use in a serial communication link uses timing information generated by a phase detector of a clock and data recovery circuit of the serial communication link and a frequency pattern of the recovered data to determine whether the data received over the serial communication link is over-equalized or under-equalized. The equalizer strength of the adaptive equalizer system is adjusted based on such determination.
摘要翻译：用于串行通信链路的自适应均衡器系统使用由串行通信链路的时钟和数据恢复电路的相位检测器产生的定时信息和恢复数据的频率模式，以确定通过串行通信链路接收的数据过度平衡或欠平衡。基于这样的判定来调整自适应均衡器系统的均衡器强度。

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