专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07627044B2 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US07627044B2
公开(公告)日：2009-12-01
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Jun Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

2. 发明申请

US20070098112A1 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US20070098112A1
公开(公告)日：2007-05-03
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04L27/04 , H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

3. 发明授权

US07602253B2 Adaptive bandwidth phase locked loop with feedforward divider 有权
标题翻译：带前馈分频器的自适应带宽锁相环
公开(公告)号：US07602253B2
公开(公告)日：2009-10-13
申请号：US11637254
申请日：2006-12-11
申请人： Jaeha Kim , Deog-Kyoon Jeong
发明人： Jaeha Kim , Deog-Kyoon Jeong
IPC分类号： H03L7/00
CPC分类号： H03L7/23 , H03L7/0895 , H03L7/093 , H03L7/0995
摘要： In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括第一和第二子锁相环（sub-PLL），其包括第一和第二压控振荡器（VCO），以提供第一和第二VCO输出信号，以及第一和第二前馈分配器电路以分开第一和第二频率的第一和第二VCO输出信号通过第一和第二分频因子。该芯片还包括用于选择第一和第二分频因子的锁相环控制电路。描述和要求保护其他实施例。

4. 发明申请

US20080136531A1 Adaptive bandwidth phase locked loop with feedforward divider 有权
标题翻译：带前馈分频器的自适应带宽锁相环
公开(公告)号：US20080136531A1
公开(公告)日：2008-06-12
申请号：US11637254
申请日：2006-12-11
申请人： Jaeha Kim , Deog-Kyoon Jeong
发明人： Jaeha Kim , Deog-Kyoon Jeong
IPC分类号： H03L7/07
CPC分类号： H03L7/23 , H03L7/0895 , H03L7/093 , H03L7/0995
摘要： In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括第一和第二子锁相环（sub-PLL），其包括第一和第二压控振荡器（VCO），以提供第一和第二VCO输出信号，以及第一和第二前馈分配器电路以分开第一和第二频率的第一和第二VCO输出信号通过第一和第二分频因子。该芯片还包括用于选择第一和第二分频因子的锁相环控制电路。描述和要求保护其他实施例。

5. 发明授权

US08362642B2 Optimized power supply for an electronic system 有权
标题翻译：优化电子系统的电源
公开(公告)号：US08362642B2
公开(公告)日：2013-01-29
申请号：US12528566
申请日：2008-02-28
申请人： Jared LeVan Zerbe , Jaeha Kim , Yohan U. Frans , Huy M. Nguyen
发明人： Jared LeVan Zerbe , Jaeha Kim , Yohan U. Frans , Huy M. Nguyen
IPC分类号： H02J1/10
CPC分类号： G05F1/10 , G06F1/26 , Y10T307/406 , Y10T307/50
摘要： A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.
摘要翻译：根据与有线通信链路相关联的性能度量来调整与有线通信链路耦合的电子设备的电压供应的方法。基于性能度量产生电压调整信号。然后，电压调整信号用于更新对电子设备的电压供应。

6. 发明授权

US08279976B2 Signaling with superimposed differential-mode and common-mode signals 有权
标题翻译：信号叠加差分模式和共模信号
公开(公告)号：US08279976B2
公开(公告)日：2012-10-02
申请号：US12739938
申请日：2008-10-28
申请人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Hae-Chang Lee , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H03K9/00
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g., —the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。提取的数据信号具有与提取的时钟信号的频率相对应的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

7. 发明授权

US08159274B2 Signaling with superimposed clock and data signals 有权
标题翻译：信号叠加时钟和数据信号
公开(公告)号：US08159274B2
公开(公告)日：2012-04-17
申请号：US12739936
申请日：2008-10-28
申请人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
发明人： Qi Lin , Jaeha Kim , Brian S. Leibowitz , Jared L. Zerbe , Jihong Ren
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H04L7/0008 , H04L7/065 , H04L25/0276 , H04L25/14
摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
摘要翻译：数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。第一速率是第二速率的倍数，其中倍数大于1。数据传输电路还包括与符号时钟同步的数据驱动器。数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。数据信号和时钟信号同时被驱动到一个或多个传输线上。

8. 发明申请

US20100102868A1 Hardware and Method to Test Phase Linearity of Phase Synthesizer 失效
标题翻译：测试相位合成器的相位线性度的硬件和方法
公开(公告)号：US20100102868A1
公开(公告)日：2010-04-29
申请号：US12531830
申请日：2008-03-14
申请人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
发明人： Jaeha Kim , Hae-Chang Lee , Thomas H. Greer, III
IPC分类号： G06F1/04
CPC分类号： H03M1/109 , G01R31/31725 , G01R31/31726 , G01R31/31727 , H03M1/66
摘要： A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.
摘要翻译：用于测试相位合成器的相位线性度的电路，其合成具有相应于输入到相位合成器的数字相位值的相位的输出时钟。数字计数器向相位合成器提供数字相位值。数字计数器接收与输入时钟同步的计数器时钟。数字相位值由数字计数器步进，从而移位输出时钟的频率。对相位合成器的相位线性度分析输出时钟，以产生相位线性分析输出。

9. 发明申请

US20100085123A1 INJECTION-LOCKED CLOCK MULTIPLIER 审中-公开
标题翻译：注射锁定时间累加器
公开(公告)号：US20100085123A1
公开(公告)日：2010-04-08
申请号：US12577027
申请日：2009-10-09
申请人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Jaeha Kim
发明人： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Jaeha Kim
IPC分类号： H03L7/24
CPC分类号： H03L7/083 , H03L7/099 , H03L7/18
摘要： Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, on injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one.
摘要翻译：描述时钟电路的实施例。该时钟电路包括振荡器，其包括具有谐振频率的谐振电路，该谐振电路输出具有第一频率的第一时钟信号。此外，数字控制器耦合到振荡器。该数字控制器在时钟电路的第一操作模式期间修改振荡器的谐振频率，并且在时钟电路的第二操作模式期间中止修改。另外，注入电路耦合到振荡器。该注入电路向振荡器提供具有第二频率的第二时钟信号。注意，第二时钟信号注入锁定第一时钟信号的相位和/或第一频率。还要注意，第一频率与第二频率的比率大于或等于1。

10. 发明授权

US08289032B2 Integrated circuit having receiver jitter tolerance (“JTOL”) measurement 有权
标题翻译：具有接收机抖动容限（JTOL）测量的集成电路
公开(公告)号：US08289032B2
公开(公告)日：2012-10-16
申请号：US12529320
申请日：2008-03-19
申请人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
发明人： Hae-Chang Lee , Jaeha Kim , Brian Leibowitz
IPC分类号： G01R29/26
CPC分类号： G01R29/26 , G01R31/31709 , G01R31/31725
摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
摘要翻译：能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样。从接收器输出的采样数据值用于评估集成电路的抖动容限。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式