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1. 发明授权

US07214609B2 Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities 有权
标题翻译：用于形成单镶嵌通孔或沟槽的方法以及通过空腔形成双镶嵌
公开(公告)号：US07214609B2
公开(公告)日：2007-05-08
申请号：US10313491
申请日：2002-12-05
申请人： Ping Jiang , Rob Kraft , Guoqiang Xing , Karen H. R. Kirmse , Eden Zielinski
发明人： Ping Jiang , Rob Kraft , Guoqiang Xing , Karen H. R. Kirmse , Eden Zielinski
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76802
摘要： Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.
摘要翻译：公开了用于在单个镶嵌互连结构中形成沟槽或通孔腔的方法，包括蚀刻介电层以在其中形成空腔并暴露下面的蚀刻停止层，以及蚀刻暴露的蚀刻停止层以延伸空腔，并且暴露现有互连结构中的导电特征，其中蚀刻介电层的一部分并蚀刻蚀刻停止层的暴露部分同时进行，其间基本上没有中间处理步骤。还公开了在双镶嵌互连结构中形成通孔腔的方法，包括在现有互连结构上形成蚀刻停止层，在蚀刻停止层上形成电介质层，蚀刻介电层的一部分以形成并且暴露蚀刻停止层的一部分，以及蚀刻蚀刻停止层以延伸通孔腔，其中介电层在蚀刻停止层的蚀刻期间被覆盖。

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