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1. 发明授权

US07207017B1 Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results 有权
标题翻译：计量配方生成方法和系统，设计，模拟和计量结果的审查和分析
公开(公告)号：US07207017B1
公开(公告)日：2007-04-17
申请号：US10865047
申请日：2004-06-10
申请人： Cyrus Tabery , Chris Haidinyak , Todd P. Lukanc , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus Tabery , Chris Haidinyak , Todd P. Lukanc , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.
摘要翻译：生成计量配方的方法包括识别设备布局内的感兴趣区域。可以提供对应于所识别的感兴趣区域的坐标列表并用于创建剪切布局，其可以由剪切布局数据文件表示。裁剪的布局数据文件和相应的坐标列表可以被提供并转换成用于在测试处理的晶片和/或掩模版时引导一个或多个计量仪器的计量配方。根据测量要求收到的实验测量结果可以与相应的设计数据和仿真数据相关联，并存储在可数据库系统中。

2. 发明申请

US20050229125A1 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US20050229125A1
公开(公告)日：2005-10-13
申请号：US10816764
申请日：2004-04-02
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

3. 发明申请

US20070209030A1 SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES 有权
标题翻译：使用光学规则检查分辨率增强技术的集成电路设备和制造的系统和方法
公开(公告)号：US20070209030A1
公开(公告)日：2007-09-06
申请号：US11741845
申请日：2007-04-30
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

4. 发明申请

US20050221233A1 System and method for fabricating contact holes 有权
标题翻译：制造接触孔的系统和方法
公开(公告)号：US20050221233A1
公开(公告)日：2005-10-06
申请号：US10817193
申请日：2004-04-02
申请人： Anna Minvielle , Cyrus Tabery , Hung-eil Kim , Jongwook Kye
发明人： Anna Minvielle , Cyrus Tabery , Hung-eil Kim , Jongwook Kye
IPC分类号： G03F7/20 , G03F7/00
CPC分类号： G03F7/70425 , G03F7/70091 , G03F7/701 , G03F7/70125 , G03F7/70158
摘要： A method of forming a plurality of contact holes of varying pitch and density in a contact layer of an integrated circuit device is provided. The plurality of contact holes can include a plurality of regularly spaced contact holes having a first pitch along a first direction and a plurality of semi-isolated contact holes having a second pitch along a second direction. A double-dipole illumination source can transmit light energy through a mask having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source can include a first dipole aperture, which is oriented and optimized for patterning the regularly spaced contact holes, and a second dipole aperture, which is oriented substantially orthogonal to the first dipole aperture and optimized for patterning the plurality of semi-isolated contact holes. The contact layer can be etched using the patterned photoresist layer.
摘要翻译：提供了一种在集成电路器件的接触层中形成多个具有不同间距和密度的接触孔的方法。多个接触孔可以包括沿着第一方向具有第一间距的多个规则间隔的接触孔和沿第二方向具有第二间距的多个半隔离接触孔。双偶极照明源可以通过具有对应于期望的接触孔图案的图案的掩模传输光能。双偶极照明源可以包括第一偶极孔，其被定向和优化以用于图案化规则间隔的接触孔，以及第二偶极孔，其基本上垂直于第一偶极孔定向并且被优化用于图案化多个半隔离接触孔。可以使用图案化的光致抗蚀剂层来蚀刻接触层。

5. 发明申请

US20050104091A1 Self aligned damascene gate 有权
标题翻译：自对准镶嵌门
公开(公告)号：US20050104091A1
公开(公告)日：2005-05-19
申请号：US10699887
申请日：2003-11-04
申请人： Cyrus Tabery , Shibly Ahmed , Matthew Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Cyrus Tabery , Shibly Ahmed , Matthew Buynoski , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L21/336 , H01L29/786 , H01L29/745
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7842
摘要： A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin in the fin area, and forming a mask in the fin area. The method further includes etching the mask to expose a channel area of the MOSFET, etching the fin to thin a width of the fin in the channel area, forming a gate over the fin, and forming contacts to the gate, the source region, and the drain region.
摘要翻译：一种形成金属氧化物半导体场效应晶体管（MOSFET）的方法包括在衬底上构图翅片区域，源极区域和漏极区域，在翅片区域中形成鳍片，并在鳍片区域中形成掩模。该方法还包括蚀刻掩模以暴露MOSFET的沟道区域，蚀刻鳍以在沟道区域中减薄翅片的宽度，在鳍上方形成栅极，以及形成与栅极，源区和漏极区域。

6. 发明授权

US06835662B1 Partially de-coupled core and periphery gate module process 有权
标题翻译：部分解耦核心和周边门模块工艺
公开(公告)号：US06835662B1
公开(公告)日：2004-12-28
申请号：US10619797
申请日：2003-07-14
申请人： Jeff P. Erhardt , Hiroyuki Kinoshita , Cyrus Tabery
发明人： Jeff P. Erhardt , Hiroyuki Kinoshita , Cyrus Tabery
IPC分类号： H01L21302
CPC分类号： H01L27/11568 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/1052 , H01L27/115
摘要： The invention is an apparatus and a method of manufacturing a structure. The method includes the step of patterning a layer to include a line and space pattern. A space of the line and space pattern in a first region includes a first critical dimension less than achievable at a resolution limit of lithography. A line of the line and space pattern in a second region includes a second critical dimension achievable at a resolution limit of lithography. A sidewall spacer is formed on a line from a masking layer used in the formation of the structure. The method uses one critical masking step and two non-critical masking steps.
摘要翻译：本发明是一种制造结构的装置和方法。该方法包括图案化层以包括线和空间图案的步骤。在第一区域中的线和空间图案的空间包括在光刻的分辨率极限下小于可实现的第一临界尺寸。第二区域中的线和空间图案的线包括在光刻的分辨率极限下可实现的第二临界尺寸。在用于形成结构的掩模层的一条线上形成侧壁间隔物。该方法使用一个关键的屏蔽步骤和两个非关键的屏蔽步骤。

7. 发明授权

US06995437B1 Semiconductor device with core and periphery regions 有权
标题翻译：具有核心和外围区域的半导体器件
公开(公告)号：US06995437B1
公开(公告)日：2006-02-07
申请号：US10869774
申请日：2004-06-16
申请人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
发明人： Hiroyuki Kinoshita , Yu Sun , Basab Banerjee , Christopher M. Foster , John R. Behnke , Cyrus Tabery
IPC分类号： H01L31/119
CPC分类号： H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
摘要翻译：一种用于形成半导体器件的方法，其包括在衬底上的层中具有可变节距和临界尺寸的线和间隔图案。衬底包括第一区域（例如芯区域）和第二区域（例如，周边区域）。第一区域中的第一子线和空间图案包括尺寸（A）的空间小于单独通过光刻工艺可实现的尺寸。此外，第二区域中的第二子线和空间图案包括至少一条线，其包括通过光刻可实现的第二临界尺寸（B）。该方法使用两个关键的掩模步骤来形成硬掩模，其在芯部区域中包括小于在光刻的分辨率极限下可实现的临界尺寸（A）。此外，该方法使用单个蚀刻步骤将硬掩模的图案转移到该层。

8. 发明申请

US20050048223A1 Method and apparatus for elimination of bubbles in immersion medium in immersion lithography systems 有权
标题翻译：浸没式光刻系统中浸没介质中气泡消除的方法和装置
公开(公告)号：US20050048223A1
公开(公告)日：2005-03-03
申请号：US10653844
申请日：2003-09-02
申请人： Adam Pawloski , Amr Abdo , Gilles Amblard , Bruno LaFontaine , Ivan Lalovic , Harry Levinson , Jeffrey Schefske , Cyrus Tabery , Frank Tsai
发明人： Adam Pawloski , Amr Abdo , Gilles Amblard , Bruno LaFontaine , Ivan Lalovic , Harry Levinson , Jeffrey Schefske , Cyrus Tabery , Frank Tsai
IPC分类号： G03F7/20 , B05D3/00
CPC分类号： G03F7/70341
摘要： A method of operating an immersion lithography system, including steps of immersing at least a portion of a wafer to be exposed in an immersion medium, wherein the immersion medium comprises at least one bubble; directing an ultrasonic wave through at least a portion of the immersion medium to disrupt and/or dissipate the at least one bubble; and exposing the wafer with an exposure pattern by passing electromagnetic radiation through the immersion medium subsequent to the directing. Also disclosed is a monitoring and control system for an immersion lithography system.
摘要翻译：一种操作浸没式光刻系统的方法，包括将要曝光的晶片的至少一部分浸入浸没介质中的步骤，其中浸没介质包括至少一个气泡; 引导超声波穿过所述浸没介质的至少一部分以破坏和/或消散所述至少一个气泡; 以及在引导之后通过使电磁辐射穿过浸渍介质，以曝光图案曝光晶片。还公开了一种用于浸没式光刻系统的监视和控制系统。

9. 发明授权

US07118967B1 Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing 有权
标题翻译：保护电荷捕获电介质闪存器件免受BEOL处理中的紫外线引起的充电
公开(公告)号：US07118967B1
公开(公告)日：2006-10-10
申请号：US10368696
申请日：2003-02-19
申请人： Minh V. Ngo , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Cyrus Tabery , John Caffall , Tyagamohan Gottipati , Dawn Hopper
发明人： Minh V. Ngo , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Cyrus Tabery , John Caffall , Tyagamohan Gottipati , Dawn Hopper
IPC分类号： H01L21/336
CPC分类号： H01L29/7923 , H01L29/66833 , Y10S438/954
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.
摘要翻译：一种保护电荷捕获电介质闪存单元免受UV感应充电的方法，包括在半导体器件中制造包括电荷捕获介电电荷存储层的电荷捕获电介质闪存单元; 并且在形成电荷捕获介电电荷存储层之后的处理步骤期间，保护电荷捕获电介质闪速存储器单元暴露于足以在电荷俘获电介质闪存单元中沉积不可擦除电荷的UV辐射水平。在一个实施例中，保护步骤是通过选择不包括半导体器件的使用，产生或曝光到足以沉积不可擦除电荷的紫外线辐射的水平的BEOL制造中的工艺进行的。

10. 发明授权

US07018868B1 Disposable hard mask for memory bitline scaling 有权
标题翻译：用于存储器位线缩放的一次性硬掩模
公开(公告)号：US07018868B1
公开(公告)日：2006-03-28
申请号：US10770245
申请日：2004-02-02
申请人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
发明人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
IPC分类号： H01L21/44
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和半导体器件的制造方法。半导体器件包括在半导体衬底中的掩埋位线。此外，掺杂区域形成在掩埋位线附近。与掩埋位线相邻的掺杂区域可以防止掩埋位线之间的漏电流。

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