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1. 发明授权

US07657864B2 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US07657864B2
公开(公告)日：2010-02-02
申请号：US11741845
申请日：2007-04-30
申请人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

2. 发明授权

US07194725B1 System and method for design rule creation and selection 失效
标题翻译：设计规则创建和选择的系统和方法
公开(公告)号：US07194725B1
公开(公告)日：2007-03-20
申请号：US10817132
申请日：2004-04-02
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.
摘要翻译：一种产生设计规则的方法，包括生成多个参数变化的几何布局并且模拟每个几何布局如何在晶片上图案化。模拟几何布局中的结构边缘可以基于可制造性进行分类，并且可以创建设计规则以禁止展示不良制造性的布局。

3. 发明授权

US07071085B1 Predefined critical spaces in IC patterning to reduce line end pull back 有权
标题翻译： IC图案化中预定的关键空间，以减少线端拉回
公开(公告)号：US07071085B1
公开(公告)日：2006-07-04
申请号：US10852876
申请日：2004-05-25
申请人： Todd P. Lukanc , Luigi Capodieci , Christopher A. Spence , Joerg Reiss , Sarah N. McGowan
发明人： Todd P. Lukanc , Luigi Capodieci , Christopher A. Spence , Joerg Reiss , Sarah N. McGowan
IPC分类号： H01L21/475
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , Y10S438/947
摘要： The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.
摘要翻译：本发明包括一种制造这种设备的装置和方法，包括以下步骤：形成待图案化的层，在待图案化的层上形成感光层，使光敏层形成图案，形成包括水平线和垂直线将图案转移到待图案化的层上，在图案上形成第二感光层，图案化第二感光层以形成包括在水平线和垂直线之间对准的空间的第二图案，并且转印第二图案到要被图案化的层以形成包括水平线和在其间具有空间的垂直线的第三图案，该空间包括在光刻的分辨率极限下可实现的宽度尺寸。

4. 发明授权

US06749971B2 Method of enhancing clear field phase shift masks with chrome border around phase 180 regions 有权
标题翻译：在相位180区域附近用镀铬边框增强清除场相移掩模的方法
公开(公告)号：US06749971B2
公开(公告)日：2004-06-15
申请号：US10016710
申请日：2001-12-11
申请人： Todd P. Lukanc , Christopher A. Spence
发明人： Todd P. Lukanc , Christopher A. Spence
IPC分类号： G03F900
CPC分类号： G03F1/30 , G03F1/70
摘要： A mask generation method can enhance clear field phase shift masks using a chrome border around phase 180 regions. An exemplary method involves identifying edges of a 180 degree phase pattern, expanding these edges, and merging the expansions with chrome. An alternative method involves oversizing and undersizing phase 180 data, taking the difference, and merging the difference with chrome. The chrome region on the phase mask can improve mask generation by allowing the chrome on the mask to fully define the quartz etch.
摘要翻译：掩模生成方法可以使用围绕相位180区域的镀铬边框增强清晰的场相移掩模。一个示例性的方法包括识别180度相位图案的边缘，展开这些边缘，以及使用chrome合并展开。另一种方法是超过180度的数据，并将其与铬相结合。相位掩模上的铬区域可以通过使掩模上的铬完全限定石英蚀刻来改善掩模生成。

5. 发明授权

US06171739B2 Method of determining focus and coma of a lens at various locations in an imaging field 有权
标题翻译：在成像领域的各个位置确定透镜的焦点和彗差的方法
公开(公告)号：US06171739B2
公开(公告)日：2001-01-09
申请号：US09205792
申请日：1998-12-04
申请人： Christopher A. Spence , Regina T. Schmidt
发明人： Christopher A. Spence , Regina T. Schmidt
IPC分类号： G03F900
CPC分类号： G03F7/706
摘要： A method of determining at least one of focus and coma of a lens at a selected location in an imaging field, includes the step of forming a predetermined pattern on a mask for transference to a wafer through a lens. The pattern including a plurality of features such that a first of the plurality of features is situated adjacent a first side of a first phase shift region formed on the mask, and a second of the plurality of features is situated adjacent a second side of a second phase shift region formed on the mask, the second side being substantially opposite the first side. The method further includes the steps of transferring the pattern formed on the mask to the wafer, measuring a dimension of each of a first structure and a second structure formed on the wafer, the first structure being formed as a result of the first feature being transferred from the mask to the wafer and the second structure being formed as a result of the second feature being transferred from the mask to the wafer, and using the measured dimensions to determine the at least one of focus and coma of the lens at the selected location.
摘要翻译：一种确定成像场中选定位置处的透镜的焦点和彗差中的至少一个的方法包括在掩模上形成预定图案以通过透镜转移到晶片的步骤。所述图案包括多个特征，使得所述多个特征中的第一特征位于形成在所述掩模上的第一相移区域的第一侧附近，并且所述多个特征中的第二特征位于邻近所述掩模的第二侧面的第二侧形成在掩模上的相移区域，第二侧基本上与第一侧相对。该方法还包括以下步骤：将形成在掩模上的图案转印到晶片上，测量形成在晶片上的第一结构和第二结构中的每一个的尺寸，第一结构由于第一特征被转移而形成从所述掩模到所述晶片，并且所述第二结构是由于所述第二特征从所述掩模转移到所述晶片而形成的，并且使用所测量的尺寸来确定所述位置处的所述透镜的焦点和彗差中的至少一个。

6. 发明授权

US5930659A Forming minimal size spaces in integrated circuit conductive lines 失效
标题翻译：在集成电路导线中形成最小尺寸空间
公开(公告)号：US5930659A
公开(公告)日：1999-07-27
申请号：US986098
申请日：1997-12-05
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/321 , H01L21/768 , H01L21/3205 , H01L21/324
CPC分类号： H01L21/76888 , H01L21/32105 , H01L21/76838
摘要： A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.
摘要翻译：通过将多晶硅中期望的间隙或空间的大小的面积转换为氧化硅，然后除去氧化硅，形成多晶硅导电线图形中的最小间隙或间隔的方法，以增加集成电路的密度。优选的方法是选择性地将氧注入到多晶硅中并进行退火以将氧注入的多晶硅转化为氧化硅。作为替代方法，首先通过常规光学光刻形成覆盖在导电线上的绝缘层中的开口，随后在开口中形成侧壁以形成减小的开口，并且使用侧壁作为掩模，以通过缩小开口来覆盖氧气注入氧气并进入暴露的多晶硅导电线。在退火之后，注入的多晶硅转变成氧化硅并去除，以在多晶硅导电线图案中形成与缩小的开口大致相等的间隙或空间。代替用氧气进行全面注入，可以使用热氧化来将暴露的多晶硅转化为氧化硅。

7. 发明授权

US5601954A Attenuated phase shift mask comprising phase shifting layer with parabolically shaped sidewalls 失效
标题翻译：衰减的相移掩模包括具有抛物线形侧壁的相移层
公开(公告)号：US5601954A
公开(公告)日：1997-02-11
申请号：US469148
申请日：1995-06-05
申请人： Zoran Krivokapic , Christopher A. Spence
发明人： Zoran Krivokapic , Christopher A. Spence
IPC分类号： G03F1/32 , H01L21/027 , G03F9/00
CPC分类号： G03F1/32
摘要： An attenuated phase shift mask comprises a first layer having a thickness to provide a transmission in the range of about 3 to 10% formed on a transparent substrate and a second layer comprising a transparent material having a thickness to provide a desired phase shift, formed on said first layer. For a phase shift of 180.degree. and i-line wavelength (365 nm), where chromium is used as the first layer, then a thickness within the range of about 25 to 75 run is employed; where silicon dioxide is used as the second layer, then a thickness of about 400 to 450 nm is employed. While the oxide may be dry-etched, an isotropic wet etch provides superior aerial images.
摘要翻译：衰减相移掩模包括第一层，其具有提供在透明衬底上形成的大约3至10％范围内的透射率的厚度，以及包括具有提供期望相移的厚度的透明材料的第二层，形成在说第一层。对于使用铬作为第一层的180度和i线波长（365nm）的相移，则使用在约25至75nm范围内的厚度; 其中使用二氧化硅作为第二层，然后使用约400至450nm的厚度。虽然氧化物可以被干蚀刻，但是各向同性的湿蚀刻提供了优异的航空图像。

8. 发明授权

US07543256B1 System and method for designing an integrated circuit device 失效
标题翻译：用于设计集成电路器件的系统和方法
公开(公告)号：US07543256B1
公开(公告)日：2009-06-02
申请号：US10790590
申请日：2004-03-01
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F8/48 , G06F8/447 , G06F17/5022
摘要： A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.
摘要翻译：一种方法包括提供初始的IC器件设计，该设计具有期望的一组电特性。生成对应于初始设备设计的布局表示。仿真工具用于确定布局表示是否对应于具有所需电气特性的IC器件设计。此外，使用仿真工具评估由于工艺变化而设计的IC器件内的结构之间的变化。该变体可用于确定设计是否被优化。

9. 发明授权

US06255125B1 Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer 失效
标题翻译：用于补偿半导体晶片生产中的临界尺寸变化的方法和装置
公开(公告)号：US06255125B1
公开(公告)日：2001-07-03
申请号：US09277093
申请日：1999-03-26
申请人： Regina T. Schmidt , Christopher A. Spence , Anna M. Minvielle , Marina V. Plat , Khanh B. Nguyen
发明人： Regina T. Schmidt , Christopher A. Spence , Anna M. Minvielle , Marina V. Plat , Khanh B. Nguyen
IPC分类号： H01L2166
CPC分类号： H01L22/34
摘要： Prior to entering into manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various structures. Each of the test wafers include a substrate, an insulating layer overlying the substrate, and a semi-conductive film layer formed over the insulating layer. The film layer is comprised of, for example, poly-silicon and has a predetermined thickness which substantially corresponds to the thickness of a film layer deposited on the final production wafer. The film layer is etched to form a desired pattern of structures and implanted with a dopant to diffuse dopant atoms thoughout. Thereafter, critical dimension measurements of the structures are taken preferably using electrical line width measurements techniques. Variations in critical dimension measurements taken from the test wafer as compared to desired predetermined line width measurements are compensated for prior to manufacturing the final production wafer so as to provide circuits with the desired electrical parameters.
摘要翻译：在制造最终生产晶片之前，制造了一系列测试晶片来分析和测试各种结构。每个测试晶片包括衬底，覆盖衬底的绝缘层和形成在绝缘层上的半导电膜层。膜层由例如多晶硅构成，并且具有基本对应于沉积在最终生产晶片上的膜层的厚度的预定厚度。蚀刻膜层以形成期望的结构图案，并注入掺杂剂以扩散掺杂剂原子。此后，优选使用电线宽度测量技术来获得结构的临界尺寸测量。在制造最终生产晶片之前补偿与期望的预定线宽测量值相比，从测试晶片获取的临界尺寸测量值的变化，以便为电路提供所需的电参数。

10. 发明授权

US6146954A Minimizing transistor size in integrated circuits 失效
标题翻译：集成电路中的晶体管尺寸最小化
公开(公告)号：US6146954A
公开(公告)日：2000-11-14
申请号：US119934
申请日：1998-07-21
申请人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
发明人： Richard K. Klein , Asim A. Selcuk , Nicholas J. Kepler , Craig S. Sander , Christopher A. Spence , Raymond T. Lee , John C. Holst , Stephen C. Horne
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768 , H01L29/417
CPC分类号： H01L29/66545 , H01L21/2257 , H01L21/76895 , H01L29/41775 , H01L29/41783
摘要： A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.
摘要翻译：一种用局部互连制造半导体衬底中的场效应晶体管（FET）的方法，以便通过在FET之前和之后制造FET和局部互连件的源极和漏极来形成多晶硅栅极和局部互连之间的最小绝缘空间形成FET的栅极。在形成栅极之前去除源极和漏极之间的绝缘层的一部分。优选地，在该方法中使用在绝缘层下方的半导体衬底上的蚀刻停止层。

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