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1. 发明授权

US08445966B2 Method and apparatus for protection against process-induced charging 有权
标题翻译：用于防止过程引起的充电的方法和装置
公开(公告)号：US08445966B2
公开(公告)日：2013-05-21
申请号：US11614053
申请日：2006-12-20
申请人： David M. Rogers , Mimi X. Qian , Kwadwo A. Appiah , Mark Randolph , Michael A. VanBuskirk , Tazrien Kamal , Hiroyuki Kinoshita , Yi He , Wei Zheng
发明人： David M. Rogers , Mimi X. Qian , Kwadwo A. Appiah , Mark Randolph , Michael A. VanBuskirk , Tazrien Kamal , Hiroyuki Kinoshita , Yi He , Wei Zheng
IPC分类号： H01L23/62
CPC分类号： H01L21/768 , G11C8/08 , G11C8/14 , H01L27/0248 , H01L29/66477 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).
摘要翻译：用于改善电荷耗散保护的半导体器件（400）包括衬底（426），半导体或导电材料层（406），一个或多个薄膜器件（408）和电荷通道器件（414）。薄膜器件（408）连接到半导体或导电层（406），并且电荷通道器件（414）耦合到薄膜器件（408）和衬底（426），并提供来自薄的薄膜器件（408）到衬底（426）以将电荷从半导体/导电层（406）耗散到衬底（426）。

2. 发明授权

US07297592B1 Semiconductor memory with data retention liner 有权
标题翻译：具有数据保留衬垫的半导体存储器
公开(公告)号：US07297592B1
公开(公告)日：2007-11-20
申请号：US11195201
申请日：2005-08-01
申请人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn Hopper , Pei-Yuan Gao
发明人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn Hopper , Pei-Yuan Gao
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L21/3185 , H01L27/11568
摘要： A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.
摘要翻译：一种用于双位闪速存储器的制造方法包括提供半导体衬底和沉积电荷捕获电介质层，其中沉积是以超低沉积速率使用氨而不使用氨。植入第一和第二位线，并存放字线层。硬掩模层沉积在字线层上。光刻胶沉积在字线层上并用于形成硬掩模。去除光致抗蚀剂。使用硬掩模处理字线层以形成字线，并且去除硬掩模。减少氢，高密度数据保持衬垫以减少电荷损失，覆盖字线和电荷捕获电介质层。层间绝缘层沉积在数据保持衬里上。

3. 发明授权

US07176113B1 LDC implant for mirrorbit to improve Vt roll-off and form sharper junction 有权
标题翻译： LDC植入物用于镜像，以改善Vt滚降并形成更清晰的接合
公开(公告)号：US07176113B1
公开(公告)日：2007-02-13
申请号：US10862636
申请日：2004-06-07
申请人： Nga-Ching Alan Wong , Weidong Qian , Sameer Haddad , Mark Randolph , Mark Ramsbey , Tazrien Kamal
发明人： Nga-Ching Alan Wong , Weidong Qian , Sameer Haddad , Mark Randolph , Mark Ramsbey , Tazrien Kamal
IPC分类号： H01L21/425
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.
摘要翻译：本发明涉及在形成存储器件中实施轻掺杂通道（LDC）植入物以改善Vt滚降等。轻掺杂通道有助于保持通道完整性，使得阈值电压（Vt）可以保持在相对稳定的水平，从而减轻Vt滚降。 LDC还有助于减少掩埋位线宽度，从而使位线更靠近在一起。因此，可以在相同或更小的区域内形成或“包装”更多的装置。

4. 发明授权

US06720133B1 Memory manufacturing process using disposable ARC for wordline formation 失效
标题翻译：使用一次性ARC进行字线形成的存储器制造过程
公开(公告)号：US06720133B1
公开(公告)日：2004-04-13
申请号：US10126280
申请日：2002-04-19
申请人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
IPC分类号： G03F700
CPC分类号： H01L27/11568 , H01L27/115 , Y10S430/151
摘要： A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.
摘要翻译：集成电路的制造方法包括在芯区域上的电荷捕获材料下方具有位线的半导体衬底和在周边区域上的栅极绝缘体材料。在覆盖周边区域的同时，在芯区域上沉积并图案化字线栅极材料，硬掩模和第一光致抗蚀剂。在去除第一光致抗蚀剂之后，从芯区域中的字线栅极材料形成字线。在外围区域上沉积并图案化抗反射涂层和第二光致抗蚀剂并覆盖芯区域。防反射涂层是可去除的，而不会损坏电荷捕获材料。在去除第二光致抗蚀剂和抗反射涂层之后，栅极由周边区域中的字线栅极材料形成，并且集成电路完成。

5. 发明授权

US06620717B1 Memory with disposable ARC for wordline formation 失效
标题翻译：具有一次性ARC用于字线形成的记忆
公开(公告)号：US06620717B1
公开(公告)日：2003-09-16
申请号：US10100487
申请日：2002-03-14
申请人： Tazrien Kamal , Scott A. Bell , Kouros Ghandehari , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang
发明人： Tazrien Kamal , Scott A. Bell , Kouros Ghandehari , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang
IPC分类号： H01L213205
CPC分类号： H01L27/11568 , H01L21/32139 , H01L27/115
摘要： A method of manufacturing for a Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited. A disposable anti-reflective coating (ARC) material and a photoresist material are deposited followed by processing to form a patterned photoresist material and a patterned ARC material. The hard mask material is processed to form a patterned hard mask material. The patterned photoresist is removed and then the patterned ARC without damaging the patterned hard mask material or the wordline material. The wordline material is processed using the patterned hard mask material to form a wordline and the patterned hard mask material is removed without damaging the wordline or the charge-trapping dielectric material.
摘要翻译：一种用于闪速存储器的制造方法包括在半导体衬底上沉积电荷捕获材料并植入第一和第二位线。字线材料沉积在电荷捕获电介质材料上并沉积硬掩模材料。沉积一次性抗反射涂层（ARC）材料和光致抗蚀剂材料，然后进行处理以形成图案化的光致抗蚀剂材料和图案化的ARC材料。加工硬掩模材料以形成图案化的硬掩模材料。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏图案化的硬掩模材料或字线材料。使用图案化的硬掩模材料处理字线材料以形成字线，并且去除图案化的硬掩模材料而不损坏字线或电荷捕获电介质材料。

6. 发明授权

US07811915B2 Method for forming bit lines for semiconductor devices 有权
标题翻译：用于形成半导体器件的位线的方法
公开(公告)号：US07811915B2
公开(公告)日：2010-10-12
申请号：US12048549
申请日：2008-03-14
申请人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
发明人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L21/22
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.
摘要翻译：一种形成半导体器件的方法包括在衬底的第一部分上形成第一介电层，在第一介电层上形成电荷存储层，并蚀刻电荷存储层和第一介电层中的沟槽，其中沟槽延伸到基底。该方法还包括将n型杂质注入到衬底中以形成具有第一深度和第一宽度的n型区域，并且在植入n型杂质之后将p型杂质注入到衬底中，形成p型杂质具有第二深度和第二宽度的p型区域。该方法还包括在电荷存储层上形成第二电介质层，并在第二电介质层上形成控制栅极。

7. 发明授权

US07163860B1 Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device 有权
标题翻译：在电荷捕获电介质闪速存储器件中形成具有降低的氢含量的栅堆叠间隔物和电荷储存材料的方法
公开(公告)号：US07163860B1
公开(公告)日：2007-01-16
申请号：US10430471
申请日：2003-05-06
申请人： Tazrien Kamal , Yun Wu , Mark Ramsbey , Jean Yee-Mei Yang , Arvind Halliyal , Rinji Sugino , Hidehiko Shiraiwa , Fred T K Cheung
发明人： Tazrien Kamal , Yun Wu , Mark Ramsbey , Jean Yee-Mei Yang , Arvind Halliyal , Rinji Sugino , Hidehiko Shiraiwa , Fred T K Cheung
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L29/7923 , Y10S438/954
摘要： The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.
摘要翻译：本发明在一个实施例中涉及一种用于制造电荷俘获电介质闪存器件的方法，该器件包括提供半导体衬底，该半导体衬底上形成有包括电荷俘获介电电荷存储层和覆盖电荷的控制栅电极俘获介电电荷存储层; 至少在所述栅叠层上形成氧化层; 以及在所述栅极堆叠上沉积间隔层，其中所述沉积步骤沉积相对于常规间隔物材料的氢含量具有降低的氢含量的间隔物材料。

8. 发明授权

US07023046B2 Undoped oxide liner/BPSG for improved data retention 有权
标题翻译：未掺杂氧化物衬垫/ BPSG，以改善数据保留
公开(公告)号：US07023046B2
公开(公告)日：2006-04-04
申请号：US10617450
申请日：2003-07-11
申请人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
发明人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31612 , H01L21/31625 , H01L27/115 , H01L29/511
摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.
摘要翻译：具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在相同的沉积室。

9. 发明授权

US06927145B1 Bitline hard mask spacer flow for memory cell scaling 有权
标题翻译：位线硬掩模间隔流程用于存储单元缩放
公开(公告)号：US06927145B1
公开(公告)日：2005-08-09
申请号：US10770673
申请日：2004-02-02
申请人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
发明人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
IPC分类号： H01L21/027 , H01L21/761 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和形成半导体器件的方法。半导体器件包括衬底; 在衬底中形成的掩埋位线比在光刻的分辨率极限下可实现的更窄; 与所述掩埋位线中的至少一个相邻地形成的掺杂区域; 设置在所述基板上的电荷捕获层; 以及设置在所述电荷俘获层上的导电层，其中与所述掩埋位线中的至少一个相邻的所述掺杂区域抑制所述掩埋位线之间的漏电流。

10. 发明授权

US06912163B2 Memory device having high work function gate and method of erasing same 有权
标题翻译：具有高功函数门的存储器件及其擦除方法
公开(公告)号：US06912163B2
公开(公告)日：2005-06-28
申请号：US10658506
申请日：2003-09-09
申请人： Wei Zheng , Yun Wu , Hidehiko Shiraiwa , Mark T. Ramsbey , Tazrien Kamal
发明人： Wei Zheng , Yun Wu , Hidehiko Shiraiwa , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： H01L29/7923 , H01L29/7887
摘要： A charge trapping dielectric memory device. The memory device includes a gate electrode disposed over a dielectric stack that includes a dielectric charge trapping layer. The gate electrode has a work function of about 4.6 eV to about 5.2 eV.
摘要翻译：电荷俘获介质存储器件。存储器件包括设置在包括介电电荷捕获层的电介质叠层上的栅电极。栅电极具有约4.6eV至约5.2eV的功函数。

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