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1. 发明授权

US07657864B2 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US07657864B2
公开(公告)日：2010-02-02
申请号：US11741845
申请日：2007-04-30
申请人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
发明人： Cyrus E. Tabery , Todd P. Lukanc , Chris Haidinyak , Luigi Capodieci , Carl P. Babcock , Hung-eil Kim , Christopher A. Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

2. 发明授权

US07194725B1 System and method for design rule creation and selection 失效
标题翻译：设计规则创建和选择的系统和方法
公开(公告)号：US07194725B1
公开(公告)日：2007-03-20
申请号：US10817132
申请日：2004-04-02
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.
摘要翻译：一种产生设计规则的方法，包括生成多个参数变化的几何布局并且模拟每个几何布局如何在晶片上图案化。模拟几何布局中的结构边缘可以基于可制造性进行分类，并且可以创建设计规则以禁止展示不良制造性的布局。

3. 发明授权

US06811932B1 Method and system for determining flow rates for contact formation 失效
标题翻译：确定接触形成流量的方法和系统
公开(公告)号：US06811932B1
公开(公告)日：2004-11-02
申请号：US10165383
申请日：2002-06-06
申请人： Hung-Eil Kim
发明人： Hung-Eil Kim
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F1/44
摘要： A method and system for determining a mask for fabricating semiconductor device is described. The method and system include patterning a resist layer on at least one mask material to provide a patterned resist layer. The patterned resist layer has a plurality of apertures therein. The plurality of apertures is for the plurality of features. The plurality of apertures has a plurality of apertures sizes and a plurality of aperture pitches. The method and system also include providing a test mask for a plurality of features using the resist layer. The test mask has the plurality of apertures therein. The method and system also include determining a plurality of flow rates for the plurality of aperture pitches and the plurality of aperture sizes based upon the plurality of features.
摘要翻译：描述了一种用于确定用于制造半导体器件的掩模的方法和系统。该方法和系统包括在至少一种掩模材料上图案化抗蚀剂层以提供图案化的抗蚀剂层。图案化的抗蚀剂层在其中具有多个孔。多个孔用于多个特征。多个孔具有多个孔径和多个孔径。该方法和系统还包括使用抗蚀剂层提供多个特征的测试掩模。测试掩模在其中具有多个孔。该方法和系统还包括基于多个特征来确定多个孔距和多个孔径尺寸的多个流量。

4. 发明授权

US06576376B1 Tri-tone mask process for dense and isolated patterns 有权
标题翻译：三色蒙版过程，用于密集和孤立的图案
公开(公告)号：US06576376B1
公开(公告)日：2003-06-10
申请号：US09778586
申请日：2001-02-07
申请人： Hung-Eil Kim
发明人： Hung-Eil Kim
IPC分类号： G03F900
CPC分类号： G03F1/32
摘要： An exemplary embodiment of the disclosure relates to a method of integrated circuit fabrication involving phase shifting materials. This method can include providing a layer of chrome; providing a layer of phase shifting material over the layer of chrome; providing open spaces in the layer of chrome and layer of phase shifting material according to a pattern; removing selected open spaces proximate other open spaces; and transferring the pattern of spaces to the integrated circuit wafer. The portion of the pattern removed by the removing step is transferred to the integrated circuit wafer by side lobe printing.
摘要翻译：本公开的示例性实施例涉及涉及相移材料的集成电路制造的方法。这种方法可以包括提供一层铬; 在铬层上提供一层相移材料; 根据图案在铬层和相移材料层中提供开放空间; 移除其他开放空间附近的选定开放空间; 并将空间图案转移到集成电路晶片。通过去除步骤除去的图案的部分通过旁瓣印刷转印到集成电路晶片。

5. 发明授权

US06566020B2 Dark field trench in an alternating phase shift mask to avoid phase conflict 有权
公开(公告)号：US06566020B2
公开(公告)日：2003-05-20
申请号：US09844015
申请日：2001-04-27
申请人： Hung-Eil Kim
发明人： Hung-Eil Kim
IPC分类号： G03F900
CPC分类号： G03F1/30
摘要： A photoresist mask used in the fabrication of an integrated circuit is described. This mask can include a first portion having a phase characteristic; a second portion being located proximate the first portion and having the same phase characteristic as the first portion; and a segment disposed between the first portion and the second portion to prevent phase conflict between the first portion and the second portion.

6. 发明授权

US5817437A Method for detecting phase error of a phase shift mask 失效
标题翻译：用于检测相移掩模的相位误差的方法
公开(公告)号：US5817437A
公开(公告)日：1998-10-06
申请号：US725162
申请日：1996-10-03
申请人： Chang Nam Ahn , Hung Eil Kim
发明人： Chang Nam Ahn , Hung Eil Kim
IPC分类号： G03F1/34 , G03F1/68 , G03F1/84 , H01L21/027 , G03F9/00
CPC分类号： G03F1/30 , G03F1/84
摘要： A method for detecting the phase error of a phase shift mask simply and with ease is disclosed and comprises the steps of: arranging a plurality of phase shift patterns, each having a predetermined width and serving to shift the light transmitted through predetermined regions of a transparent substrate of the phase shift mask, at a regular space on the transparent substrate; arranging a pattern for detecting phase error in which a light screen with a predetermined width is located between the predetermined regions of the transparent substrate and the phase shift mask; patterning a wafer by use of the phase shift mask and the patterns for detecting phase error; comparing the sizes by defocuses of the patterns in which phase is shifted with those of the patterns in which phase is not shifted; and utilizing the difference in the pattern size to detect the phase error.
摘要翻译：公开了一种用于简单且容易地检测相移掩模的相位误差的方法，包括以下步骤：布置多个相移图案，每个相移图案具有预定的宽度，并用于使透过透明的预定区域的光移动在透明基板上的规则空间处的相移掩模的衬底; 布置用于检测相位误差的图案，其中具有预定宽度的光屏位于透明基板的预定区域和相移掩模之间; 通过使用相移掩模和用于检测相位误差的图案来构图晶片; 通过相位移动的图案的散焦与相位不移动的图案的尺寸比较尺寸; 并利用图案尺寸的差异来检测相位误差。

7. 发明授权

US07507661B2 Method of forming narrowly spaced flash memory contact openings and lithography masks 有权
标题翻译：形成窄间隔闪存接触开口和光刻掩模的方法
公开(公告)号：US07507661B2
公开(公告)日：2009-03-24
申请号：US10916167
申请日：2004-08-11
申请人： Emmanuil H. Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
发明人： Emmanuil H. Lingunis , Ning Cheng , Mark Ramsbey , Kouros Ghandehari , Anna Minvielle , Hung-Eil Kim
IPC分类号： H01L21/44
CPC分类号： H01L27/11568 , G03F1/36 , H01L27/115 , Y10S438/942 , Y10S438/947
摘要： A method is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.
摘要翻译：提供了一种用于在光刻掩模上产生光学特征的方法，用于在半导体器件晶片上图案化一系列蚀刻掩模的开口，包括沿着第一方向在光刻掩模上彼此间隔开的一系列光学特征，其中各个光学特征具有沿着第一方向的第一掩模特征尺寸，其小于用于在蚀刻掩模中图案化的开口的期望的第一尺寸。

8. 发明授权

US07422828B1 Mask CD measurement monitor outside of the pellicle area 有权
标题翻译：面罩CD测量显示器外面的防护薄膜区域
公开(公告)号：US07422828B1
公开(公告)日：2008-09-09
申请号：US10774099
申请日：2004-02-06
申请人： Hung-eil Kim
发明人： Hung-eil Kim
IPC分类号： G03F1/14 , G06K9/00 , G01N21/956
CPC分类号： G03F1/64 , G03F1/44 , G03F1/84 , H01L22/12
摘要： A method of fabricating a photomask having a pellicle on a photomask substrate that facilitates accurate measurement of a critical dimension on the photomask, without requiring removal of the pellicle from the photomask substrate. A first pattern is transferred onto the photomask substrate in a first area, and at least one test pattern is transferred onto the photomask substrate outside of the first area. The pellicle is attached to the photomask substrate, wherein the pellicle covers the first area, but does not cover the at least one test pattern.
摘要翻译：一种在光掩模基板上制造具有防护薄膜的光掩模的方法，其有助于精确测量光掩模上的临界尺寸，而不需要从光掩模基板去除防护薄膜。将第一图案转移到第一区域中的光掩模基板上，并且至少一个测试图案被转印到第一区域外的光掩模基板上。防护薄膜组件附接到光掩模基底，其中防护薄膜组件覆盖第一区域，但不覆盖至少一个测试图案。

9. 发明授权

US07313769B1 Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin 有权
标题翻译：通过考虑布局交互以及额外的可制造性边际来优化集成电路布局
公开(公告)号：US07313769B1
公开(公告)日：2007-12-25
申请号：US10790381
申请日：2004-03-01
申请人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
发明人： Todd P. Lukanc , Cyrus E. Tabery , Luigi Capodieci , Carl Babcock , Hung-Eil Kim , Christopher A. Spence , Chris Haidinyak
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.
摘要翻译：产生对应于集成电路（IC）设备设计的布局表示的方法可以包括根据预定的一组设计规则生成初始布局表示，并且模拟初始布局表示中的结构如何在晶片上进行图案化。基于模拟，可以识别布局表示的部分，其包括展示不良可制造性的结构和/或其中存在额外的可制造裕度的布局表示的部分。可以修改布局表示的部分，包括显示不良可制造性的结构和/或存在额外的可制造性裕度的部分，以优化布局表示。

10. 发明申请

US20090209107A1 METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING FEATURES WITHIN A MASK AND A SELECTIVE REMOVAL PROCESS 有权
标题翻译：形成电子装置的方法，包括在掩模中形成特征和选择性去除过程
公开(公告)号：US20090209107A1
公开(公告)日：2009-08-20
申请号：US12031458
申请日：2008-02-14
申请人： Todd Lukanc , Hung-Eil Kim
发明人： Todd Lukanc , Hung-Eil Kim
IPC分类号： H01L21/306
CPC分类号： H01L21/32139 , H01L21/32137
摘要： A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature.
摘要翻译：形成电子器件的方法可以包括形成覆盖下层的图案化掩模层，使得掩模层具有第一特征，第二特征和第三特征，并且第一特征位于第二特征和第三特征之间。第一特征可以通过掩模层中的第一开口与第二特征间隔开，并且可以通过掩模层中的第二开口与第三特征间隔开。该方法还可以包括选择性地移除第一开口，第二开口，第二特征和第三特征之下的下层的部分，并且还移除第二特征和第三特征，同时留下基本上所有的第一特征和第一个特征下的下层的重要部分。

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