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    • 1. 发明授权
    • Methods of making jogged layout routings double patterning compliant
    • 制作慢跑布局布线的方法双重图案化
    • US08802574B2
    • 2014-08-12
    • US13418895
    • 2012-03-13
    • Lei YuanJongwook Kye
    • Lei YuanJongwook Kye
    • H01L21/302
    • H01L21/0274G03F1/70
    • One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively.
    • 本文公开的一种说明性方法包括创建包括具有连接第一和第二线部分的交叉区域的奇点运动特征的整体目标图案,其中,交叉区域具有大于第二尺寸的第一方向上的第一尺寸, 横向于第一方向,将总体目标图案分解为第一子目标图案和第二子目标图案,其中每个子目标图案包括线路部分和交叉区域的第一部分,并且产生 分别对应于第一和第二子目标图案的第一和第二组掩模数据。
    • 2. 发明授权
    • Methods for fabricating semiconductor devices
    • 制造半导体器件的方法
    • US08361335B2
    • 2013-01-29
    • US12480232
    • 2009-06-08
    • Yunfei DengJongwook Kye
    • Yunfei DengJongwook Kye
    • B44C1/22H01L21/302
    • G03F1/00G03B27/42G03F7/2024H01L21/0273
    • Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.
    • 提供了制造半导体器件的方法。 一种方法包括提供具有第一多边形的第一图案,所述第一多边形具有第一音调并且具有第一侧和第二侧,所述第一侧邻近于具有第二音调的第二多边形,并且所述第二侧相邻于第三多边形 具有第二色调的多边形,并且通过反转第一图案的色调来形成第二图案。 该方法还包括通过从第二图案将第二多边形从第一图案转换成第二色调而将第二多边形从第一色调转换成第二色调以从第二图案转换成第二色调,从第二图案形成第三图案, 通过颠倒第三图案的音调,并通过反转第四图案的音调形成第六图案。
    • 4. 发明申请
    • MULTIPLE EXPOSURE TECHNIQUE USING OPC TO CORRECT DISTORTION
    • 使用OPC纠正错误的多次曝光技术
    • US20090040483A1
    • 2009-02-12
    • US11834979
    • 2007-08-07
    • Yunfei DengJongwook KyeRyoung-han Kim
    • Yunfei DengJongwook KyeRyoung-han Kim
    • G03B27/42G03B27/68
    • G03B27/42
    • Accurate ultrafine patterns are formed using a multiple exposure technique comprising implementing an OPC procedure to form an exposure reticle to compensate for distortion of an overlying resist pattern caused by an underlying resist pattern. Embodiments include forming a first resist pattern in a first resist layer over a target layer using a first exposure reticle, forming a second exposure reticle by an OPC technique to compensate for distortion of a second resist pattern caused by the underlying first resist pattern, depositing a second resist layer on the first resist pattern, forming the second resist pattern in the second resist layer using the second exposure reticle, the first and second resist patterns constituting a final resist mask, and forming a pattern in the target layer using the final resist mask.
    • 使用多重曝光技术形成精确的超细纹图案,该技术包括实施OPC程序以形成曝光掩模版,以补偿由下面的抗蚀剂图案引起的上覆抗蚀剂图案的变形。 实施例包括使用第一曝光掩模在目标层上在第一抗蚀剂层中形成第一抗蚀剂图案,通过OPC技术形成第二曝光掩模版,以补偿由下面的第一抗蚀剂图案引起的第二抗蚀剂图案的变形, 在第一抗蚀剂图案上的第二抗蚀剂层,使用第二曝光掩模在第二抗蚀剂层中形成第二抗蚀剂图案,第一和第二抗蚀剂图案构成最终抗蚀剂掩模,并且使用最终抗蚀剂掩模在目标层中形成图案 。
    • 9. 发明授权
    • Test structures for electrical linewidth measurement and processes for their formation
    • 电线宽测量的测试结构及其形成过程
    • US06399401B1
    • 2002-06-04
    • US09912186
    • 2001-07-24
    • Jongwook KyeHarry Levinson
    • Jongwook KyeHarry Levinson
    • G01R3126
    • H01L22/34H01L2924/0002Y10S977/88Y10S977/887H01L2924/00
    • In a method of determining a linewidth of a polysilicon line formed by a lithographic process, a polysilicon layer is formed on a substrate. A line is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure is patterned from said polysilicon layer. N2 is then implanted into the polysilicon line and the polysilicon Van der Pauw structure to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line and the polysilicon Van der Pauw structure and the dopant is activated. A sheet resistivity of the Van der Pauw structure is determined, and the linewidth of the polysilicon line is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure as the sheet resistivity of the polysilicon line. A related test structure is also disclosed.
    • 在确定通过光刻工艺形成的多晶硅线的线宽的方法中,在衬底上形成多晶硅层。 使用所述光刻工艺从所述多晶硅层图案化线,并且从所述多晶硅层构图范德波瓦结构。 然后将N 2注入到多晶硅线和多晶硅Van der Pauw结构中以形成耗尽势垒。 P型掺杂剂被注入到多晶硅线中,并且多晶硅Van der Pauw结构和掺杂剂被激活。 确定Van der Pauw结构的薄层电阻率,然后通过使用Van der Pauw结构的薄层电阻率作为多晶硅线的薄层电阻率的电线宽测量来确定多晶硅线的线宽。 还公开了相关的测试结构。