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1. 发明授权

US06828199B2 Monos device having buried metal silicide bit line 有权
标题翻译：具有埋置金属硅化物位线的单体器件
公开(公告)号：US06828199B2
公开(公告)日：2004-12-07
申请号：US10022798
申请日：2001-12-20
申请人： Jusuke Ogura , Mark T. Ramsbey , Arvind Halliyal , Zoran Krivokapic , Minh Van Ngo , Nicholas H. Tripisas
发明人： Jusuke Ogura , Mark T. Ramsbey , Arvind Halliyal , Zoran Krivokapic , Minh Van Ngo , Nicholas H. Tripisas
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/743 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.
摘要翻译：用于制造该器件的MONOS器件和方法具有形成在衬底上的电荷捕获介电层，例如氧化物 - 氮化物 - 氧化物（ONO）层。通过ONO层和衬底产生凹陷。在凹部中形成金属硅化物位线，并且在金属硅化物的顶部上形成位线氧化物。在ONO层和位线氧化物之间形成字线，并且在字线的顶部提供低电阻硅化物。硅化物例如由激光热退火形成。

2. 发明授权

US06798002B1 Dual-purpose anti-reflective coating and spacer for flash memory and other dual gate technologies and method of forming 有权
标题翻译：双用途抗反射涂层和闪存间隔器等双栅技术及成型方法
公开(公告)号：US06798002B1
公开(公告)日：2004-09-28
申请号：US09607675
申请日：2000-06-30
申请人： Robert B. Ogle, Jr. , Tuan D. Pham , Mark T. Ramsbey
发明人： Robert B. Ogle, Jr. , Tuan D. Pham , Mark T. Ramsbey
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： A dual gate semiconductor device, such as a flash memory semiconductor device, whose plurality of dual gate sidewall spacer structure is formed by a first and second anti-reflection fabrication process. The sidewall spacers of the dual transistor gate structures in the core memory region are left coated with the second anti-reflective coating material, after being used for gate patterning, to act as sidewall spacers for use in subsequent ion implant and salicidation fabrication steps. The second anti-reflective coating material is selected from a material group such as silicon oxynitride (SiON), silicon nitride (Si3N4), and silicon germanium (SiGe), or other anti-reflective coating material having optical properties and that are compatible with the subsequent implant and salicidation steps.
摘要翻译：诸如闪存半导体器件的双栅极半导体器件，其多个双栅极侧壁间隔结构通过第一和第二抗反射制造工艺形成。核心存储器区域中的双晶体管栅极结构的侧壁间隔物在用于栅极图案化之后被第二抗反射涂层材料涂覆以用作用于后续离子注入和盐化制造步骤的侧壁间隔物。第二抗反射涂层材料选自诸如氮氧化硅（SiON），氮化硅（Si 3 N 4）和硅锗（SiGe）的材料组或具有光学性质的其它抗反射涂层材料，并且与随后的植入和盐化步骤。

3. 发明授权

US06730564B1 Salicided gate for virtual ground arrays 有权
标题翻译：用于虚拟地面阵列的闸门
公开(公告)号：US06730564B1
公开(公告)日：2004-05-04
申请号：US10217821
申请日：2002-08-12
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , Y10S438/954
摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
摘要翻译：本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。未图案化的层保护字线之间的基板不会变成水银。本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

4. 发明授权

US06720133B1 Memory manufacturing process using disposable ARC for wordline formation 失效
标题翻译：使用一次性ARC进行字线形成的存储器制造过程
公开(公告)号：US06720133B1
公开(公告)日：2004-04-13
申请号：US10126280
申请日：2002-04-19
申请人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
IPC分类号： G03F700
CPC分类号： H01L27/11568 , H01L27/115 , Y10S430/151
摘要： A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.
摘要翻译：集成电路的制造方法包括在芯区域上的电荷捕获材料下方具有位线的半导体衬底和在周边区域上的栅极绝缘体材料。在覆盖周边区域的同时，在芯区域上沉积并图案化字线栅极材料，硬掩模和第一光致抗蚀剂。在去除第一光致抗蚀剂之后，从芯区域中的字线栅极材料形成字线。在外围区域上沉积并图案化抗反射涂层和第二光致抗蚀剂并覆盖芯区域。防反射涂层是可去除的，而不会损坏电荷捕获材料。在去除第二光致抗蚀剂和抗反射涂层之后，栅极由周边区域中的字线栅极材料形成，并且集成电路完成。

5. 发明授权

US06630384B1 Method of fabricating double densed core gates in sonos flash memory 有权
标题翻译：在sonos闪存中制造双激光核心门的方法
公开(公告)号：US06630384B1
公开(公告)日：2003-10-07
申请号：US09971483
申请日：2001-10-05
申请人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
发明人： Yu Sun , Michael A. Van Buskirk , Mark T. Ramsbey
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.
摘要翻译：本发明的一个方面涉及一种形成非易失性半导体存储器件的方法，包括在衬底上形成电荷俘获电介质，所述衬底具有芯区域和外围区域; 在芯区域中的电荷俘获电介质上形成第一组存储单元栅极; 在所述第一组存储单元栅极周围形成保形绝缘材料层; 以及在所述核心区域中形成第二组存储器单元栅极，其中所述第二组存储单元栅极的每个存储单元栅极与所述第一组存储单元栅极的至少一个存储单元栅极相邻，第一组存储单元栅极与第二组存储单元栅极的至少一个存储单元栅极相邻，并且保形绝缘材料层位于每个相邻的存储单元栅极之间。

6. 发明授权

US06630383B1 Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer 有权
标题翻译：双层浮栅，用于改善浮栅和高K电介质层之间的功函数
公开(公告)号：US06630383B1
公开(公告)日：2003-10-07
申请号：US10274063
申请日：2002-10-17
申请人： Effiong Ibok , Wei Zheng , Nicholas H. Tripsas , Mark T. Ramsbey , Fred T K Cheung
发明人： Effiong Ibok , Wei Zheng , Nicholas H. Tripsas , Mark T. Ramsbey , Fred T K Cheung
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28273 , H01L29/42324 , H01L29/4958 , H01L29/51 , H01L29/511
摘要： In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.
摘要翻译：在一个实施例中，公开了制造栅叠层半导体器件的方法。该方法包括以下步骤：在p型半导体衬底上形成隧道氧化物层; 通过首先形成n型多晶硅层并对n型多晶硅层进行氮化，然后在氮化的n型多晶硅层上形成p型多晶硅层，在隧道氧化物层上形成浮栅; 以及在p型多晶硅层上形成高K绝缘层。

7. 发明授权

US06620717B1 Memory with disposable ARC for wordline formation 失效
标题翻译：具有一次性ARC用于字线形成的记忆
公开(公告)号：US06620717B1
公开(公告)日：2003-09-16
申请号：US10100487
申请日：2002-03-14
申请人： Tazrien Kamal , Scott A. Bell , Kouros Ghandehari , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang
发明人： Tazrien Kamal , Scott A. Bell , Kouros Ghandehari , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang
IPC分类号： H01L213205
CPC分类号： H01L27/11568 , H01L21/32139 , H01L27/115
摘要： A method of manufacturing for a Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited. A disposable anti-reflective coating (ARC) material and a photoresist material are deposited followed by processing to form a patterned photoresist material and a patterned ARC material. The hard mask material is processed to form a patterned hard mask material. The patterned photoresist is removed and then the patterned ARC without damaging the patterned hard mask material or the wordline material. The wordline material is processed using the patterned hard mask material to form a wordline and the patterned hard mask material is removed without damaging the wordline or the charge-trapping dielectric material.
摘要翻译：一种用于闪速存储器的制造方法包括在半导体衬底上沉积电荷捕获材料并植入第一和第二位线。字线材料沉积在电荷捕获电介质材料上并沉积硬掩模材料。沉积一次性抗反射涂层（ARC）材料和光致抗蚀剂材料，然后进行处理以形成图案化的光致抗蚀剂材料和图案化的ARC材料。加工硬掩模材料以形成图案化的硬掩模材料。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏图案化的硬掩模材料或字线材料。使用图案化的硬掩模材料处理字线材料以形成字线，并且去除图案化的硬掩模材料而不损坏字线或电荷捕获电介质材料。

8. 发明授权

US06548855B1 Non-volatile memory dielectric as charge pump dielectric 失效
标题翻译：非易失性存储介质作为电荷泵电介质
公开(公告)号：US06548855B1
公开(公告)日：2003-04-15
申请号：US10147622
申请日：2002-05-16
申请人： Mark T. Ramsbey , Arvind Halliyal , Kuo-Tung Chang , Nicholas H. Tripsas , Wei Zheng , Unsoon Kim
发明人： Mark T. Ramsbey , Arvind Halliyal , Kuo-Tung Chang , Nicholas H. Tripsas , Wei Zheng , Unsoon Kim
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11539
摘要： A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.
摘要翻译：一种用于在电力终止时保留数据的非易失性存储器件。非易失性存储器件包括至少一个存储单元和用于加速输入电压源的电荷泵。电荷泵包括至少一个电容器，其中电荷泵电容器的电介质和存储单元的电介质在相同的处理步骤期间形成。

9. 发明授权

US06455373B1 Semiconductor device having gate edges protected from charge gain/loss 有权
标题翻译：具有防止电荷增益/损耗的栅极边缘的半导体器件
公开(公告)号：US06455373B1
公开(公告)日：2002-09-24
申请号：US09834419
申请日：2001-04-12
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).
摘要翻译：在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

10. 发明授权

US06448608B1 Capping layer 有权
标题翻译：封盖层
公开(公告)号：US06448608B1
公开(公告)日：2002-09-10
申请号：US09631894
申请日：2000-08-04
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： An improved flash memory device, which comprises core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer, and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The use of a high energy dopant implant to pass through dopant through the insulating layer, the protective layer, and the oxide layer into the substrate without the use of a self aligned source etch, reduces damage to the core stacks and periphery stacks caused by various etches during the production of the flash memory device and provides insulation to reduce unwanted current leakage between the tungsten plug and the stacks.
摘要翻译：一种改进的闪速存储器件，其包括用氧化物层，保护层和绝缘层保护的芯堆叠和外围堆叠。使用高能掺杂剂注入来使掺杂剂通过绝缘层，保护层和氧化物层进入衬底以产生源区和漏区，而不使用自对准蚀刻。闪存器件具有放置在芯堆叠和外围堆叠体上的金属间介电层。将钨塞放置在金属间介电层中以提供与闪存器件的漏极的电连接。使用高能掺杂剂注入物通过掺杂剂通过绝缘层，保护层和氧化物层进入衬底而不使用自对准源蚀刻，减少了由各种不同的引线引起的芯堆叠和外围堆叠的损坏在制造闪速存储器件期间蚀刻并提供绝缘以减少钨丝塞和叠层之间的不必要的电流泄漏。

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