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1. 发明申请

US20060104111A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 有权
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：US20060104111A1
公开(公告)日：2006-05-18
申请号：US10990706
申请日：2004-11-17
申请人： Nicholas Tripsas , Colin Bill , Michael VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Cai , Suzette Pangrle , Steven Avanzino
发明人： Nicholas Tripsas , Colin Bill , Michael VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Cai , Suzette Pangrle , Steven Avanzino
IPC分类号： G11C11/36
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages
摘要翻译：本存储器结构包括第一导体，第二导体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。第一和第二二极管具有不同的阈值电压

2. 发明申请

US20070025166A1 Program/erase waveshaping control to increase data retention of a memory cell 审中-公开
标题翻译：编程/擦除波形整形控制以增加存储单元的数据保留
公开(公告)号：US20070025166A1
公开(公告)日：2007-02-01
申请号：US11191126
申请日：2005-07-27
申请人： Tzu-Ning Fang , Colin Bill , Wei Cai , David Gaun , Eugen Gershon
发明人： Tzu-Ning Fang , Colin Bill , Wei Cai , David Gaun , Eugen Gershon
IPC分类号： G11C29/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0007 , G11C13/0016 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/32 , G11C2213/71 , G11C2213/77
摘要： System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.
摘要翻译：公开了改进和控制存储单元数据保持的系统和方法。产生特定的脉冲宽度和幅度并将其施加到由至少两个电极制成的存储器单元，该至少两个电极在至少两个电极之间具有可控导电的介质。检测存储器单元中的电流，并将较低的输入脉冲发送到存储单元。下部脉冲的应用控制存储器单元的数据保持，而不会干扰存储单元的最终编程状态。

3. 发明申请

US20060268595A1 Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices 有权
标题翻译：用于编程，擦除和读取纳米尺度电阻式存储器件的页缓冲器架构
公开(公告)号：US20060268595A1
公开(公告)日：2006-11-30
申请号：US11139227
申请日：2005-05-27
申请人： Colin Bill , Wei Cai
发明人： Colin Bill , Wei Cai
IPC分类号： G11C17/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2013/0085 , G11C2207/2245
摘要： In the present method of programming and erasing the resistive memory devices of an array thereof, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices whose state is to be changed from the previous state thereof.
摘要翻译：在目前的编程和擦除其阵列的电阻式存储器件的方法中，在单个命令上，在编程和擦除功能中都提供高电流，以仅对那些状态将要从前一个变化的那些存储器件进行编程和擦除状态。

4. 发明申请

US20060215439A1 Temperature compensation of thin film diode voltage threshold in memory sensing circuit 有权
公开(公告)号：US20060215439A1
公开(公告)日：2006-09-28
申请号：US11086884
申请日：2005-03-22
申请人： Colin Bill , Wei Cai
发明人： Colin Bill , Wei Cai
IPC分类号： G11C11/00
CPC分类号： G11C13/0016 , B82Y10/00 , G11C7/04 , G11C11/5664 , G11C13/00 , G11C13/0014 , G11C2213/72 , Y10S977/943
摘要： Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit and an array core with a temperature variable select device. The array core can consist of a thin film diode in series with a nanoscale resistive memory cell. The temperature sensitive bias circuit can include a thin film diode in series with two resistors, and provides a temperature compensating bias voltage to the array core. The thin film diode of the temperature sensitive bias circuit tracks the diode of the array core, while the two resistors create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core. The compensating bias reference voltage is generated by the temperature sensitive bias circuit, duplicated by a differential amplifier, and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell.

5. 发明授权

US08638609B2 Partial local self boosting for NAND 有权
标题翻译： NAND的部分本地自增强
公开(公告)号：US08638609B2
公开(公告)日：2014-01-28
申请号：US12783351
申请日：2010-05-19
申请人： Ya-Fen Lin , Colin Bill , Takao Akaogi , Youseok Suh
发明人： Ya-Fen Lin , Colin Bill , Takao Akaogi , Youseok Suh
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.
摘要翻译：存储器系统被编程为在自增强期间具有最少的程序干扰和减少的结和通道泄漏。在将程序信号施加到所选择的字线之前，预充电偏置信号被施加到与所选字线相邻的字线，并且将通过信号施加到剩余的字线。预充电偏压信号将预充电施加到存储器单元。选择预充电偏压信号以改善与所选字线相邻的字线上的存储器单元的隔离，提高自升压效率并减少电流泄漏以防止或减少程序干扰和/或编程错误，特别是在禁止的存储器所选字线上的单元格。

6. 发明授权

US06960783B2 Erasing and programming an organic memory device and method of fabricating 有权
标题翻译：擦除和编程有机存储器件及其制造方法
公开(公告)号：US06960783B2
公开(公告)日：2005-11-01
申请号：US10436786
申请日：2003-05-13
申请人： Zhida Lan , Colin Bill , Michael A. VanBuskirk
发明人： Zhida Lan , Colin Bill , Michael A. VanBuskirk
IPC分类号： G11C11/56 , G11C13/02 , H01L35/24
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0009 , G11C13/0016 , G11C2213/15 , G11C2213/56 , G11C2213/71
摘要： An organic memory cell made of two electrodes with a selectively conductive media between the two electrodes is disclosed. The selectively conductive media contains an organic layer and passive layer. The selectively conductive media is programmed by applying bias voltages that program a desired impedance state for a memory cell. The desired impedance state represents one or more bits of information and the memory cell does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media is read by applying a current and reading the impedance of the media in order to determine the impedance state of the memory cell. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.
摘要翻译：公开了一种由在两个电极之间具有选择性导电介质的两个电极制成的有机存储单元。选择性导电介质包含有机层和无源层。选择性导电介质通过施加偏置电压来编程，该偏置电压为存储器单元编程期望的阻抗状态。期望的阻抗状态表示信息的一个或多个位，并且存储单元不需要恒定的功率或刷新周期来保持所需的阻抗状态。此外，通过施加电流并读取介质的阻抗来读取选择性导电介质，以便确定存储单元的阻抗状态。还公开了制造有机存储器件/单元的方法，使用有机存储器件/单元的方法，以及诸如包含有机存储器件/单元的计算机的器件。

7. 发明授权

US06275415B1 Multiple byte channel hot electron programming using ramped gate and source bias voltage 有权
标题翻译：使用斜坡栅极和源偏置电压的多字节通道热电子编程
公开(公告)号：US06275415B1
公开(公告)日：2001-08-14
申请号：US09416563
申请日：1999-10-12
申请人： Sameer S. Haddad , Ravi S. Sunkavalli , Wing Han Leung , John Chen , Ravi Prakash Gutala , Colin Bill , Vei-Han Chan
发明人： Sameer S. Haddad , Ravi S. Sunkavalli , Wing Han Leung , John Chen , Ravi Prakash Gutala , Colin Bill , Vei-Han Chan
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated. In another embodiment, a bias voltage is applied to the common source terminal and a bias voltage is applied to the common well voltage. The combination of the voltages applied to the control gates and to the sources decreases loading on the bitlines to ensure that VDS does not fall below a required level necessary for the maintenance of the hot carrier effect during programming. A bias voltage can also be applied to the wells of the memory cells while the common source terminal is held at ground. Feedback control of the programming gate voltages can be used to control the power required for programming.
摘要翻译：一种具有多个存储单元的存储器件，每个存储体具有多个存储器单元，以及一种编程器件中的多个存储器单元的方法，其中偏置电压施加到多个存储器单元的公共源极端子，并且将时变电压施加到要编程的存储单元。在一个实施例中，施加到要编程的存储器单元的栅极的电压是斜坡电压。在第二实施例中，施加到待编程的存储器单元的栅极的电压是增加的阶梯电压。在另一个实施例中，选择施加到公共源极端子的偏置电压和施加到要编程的存储器单元的控制栅极的电压，使得流过被编程的单元的电流减小，并且来自存储器单元的泄漏电流不被编程的基本上被消除。在另一个实施例中，将偏置电压施加到公共源极端子，并将偏置电压施加到公共井电压。施加到控制栅极和源极的电压的组合减少了位线上的负载，以确保VDS不会降低到在编程期间维持热载流子效应所需的水平。偏置电压也可以施加到存储单元的阱，同时公共源极保持在地。编程栅极电压的反馈控制可用于控制编程所需的功率。

8. 发明授权

US07259039B2 Memory device and methods of using and making the device 有权
标题翻译：内存设备和使用和制造设备的方法
公开(公告)号：US07259039B2
公开(公告)日：2007-08-21
申请号：US10818261
申请日：2004-04-02
申请人： Zhida Lan , Michael A. Van Buskirk , Colin Bill
发明人： Zhida Lan , Michael A. Van Buskirk , Colin Bill
IPC分类号： H01L51/40
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/71 , G11C2213/77 , H01L27/24 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0085 , H01L51/0595
摘要： A memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an active low conductive layer and passive layer. The controllably conductive media changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
摘要翻译：公开了由在两个电极之间具有可控导电介质的两个电极制成的存储单元。可控导电介质包含有源低导电层和无源层。当施加外部刺激（例如施加的电场）时，可控导电介质改变其阻抗。还公开了制造存储器件/单元的方法，使用存储器件/单元的方法，以及诸如包含存储器件/单元的计算机的器件。

9. 发明授权

US07028240B1 Diagnostic mode for testing functionality of BIST (built-in-self-test) back-end state machine 有权
标题翻译：用于测试BIST（内置自检）后端状态机的功能的诊断模式
公开(公告)号：US07028240B1
公开(公告)日：2006-04-11
申请号：US10200526
申请日：2002-07-22
申请人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill
发明人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill
IPC分类号： G01R3/28
CPC分类号： G11C29/02 , G11C16/04 , G11C29/16
摘要： In a method and system for diagnosing a back-end state machine used for testing flash memory cells fabricated on a semiconductor substrate, a signal selector and a diagnostic matching logic are fabricated on the semiconductor substrate. The diagnostic matching logic sets a generated match output to a pass or fail state depending on control variables from the back-end state machine. The signal selector selects the generated match output to be used in a verify step of a BIST (built-in-self-test) mode, if a diagnostic mode is invoked. The back-end state machine performs a plurality of BIST modes with the generated match output, for testing the functionality of the back-end state machine.
摘要翻译：在用于诊断用于测试在半导体衬底上制造的闪存单元的后端状态机的方法和系统中，在半导体衬底上制造信号选择器和诊断匹配逻辑。诊断匹配逻辑根据后端状态机的控制变量将生成的匹配输出设置为通过或失败状态。如果调用诊断模式，则信号选择器选择要在BIST（内置自检）模式的验证步骤中使用的生成的匹配输出。后端状态机利用生成的匹配输出执行多个BIST模式，用于测试后端状态机的功能。

10. 发明申请

US20060067105A1 Control of memory devices possessing variable resistance characteristics 有权
标题翻译：具有可变电阻特性的存储器件的控制
公开(公告)号：US20060067105A1
公开(公告)日：2006-03-30
申请号：US10983919
申请日：2004-11-08
申请人： Tzu-Ning Fang , Michael Van Buskirk , Colin Bill
发明人： Tzu-Ning Fang , Michael Van Buskirk , Colin Bill
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.
摘要翻译：采用至少一个恒定电流源的系统和方法促进有机存储器单元的编程和/或采用至少一个恒定电压源以便于擦除存储器件。本发明用于单个存储器单元装置和存储单元阵列。使用恒流源防止编程期间的电流尖峰，并允许在写周期期间精确控制存储单元的状态，而与电池的电阻无关。使用恒定电压源在擦除周期期间为存储器单元提供稳定的负载，并且允许跨过存储器单元的精确的电压控制，尽管在该过程中电池电阻的大的动态变化。

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