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1. 发明授权

US06275415B1 Multiple byte channel hot electron programming using ramped gate and source bias voltage 有权
标题翻译：使用斜坡栅极和源偏置电压的多字节通道热电子编程
公开(公告)号：US06275415B1
公开(公告)日：2001-08-14
申请号：US09416563
申请日：1999-10-12
申请人： Sameer S. Haddad , Ravi S. Sunkavalli , Wing Han Leung , John Chen , Ravi Prakash Gutala , Colin Bill , Vei-Han Chan
发明人： Sameer S. Haddad , Ravi S. Sunkavalli , Wing Han Leung , John Chen , Ravi Prakash Gutala , Colin Bill , Vei-Han Chan
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated. In another embodiment, a bias voltage is applied to the common source terminal and a bias voltage is applied to the common well voltage. The combination of the voltages applied to the control gates and to the sources decreases loading on the bitlines to ensure that VDS does not fall below a required level necessary for the maintenance of the hot carrier effect during programming. A bias voltage can also be applied to the wells of the memory cells while the common source terminal is held at ground. Feedback control of the programming gate voltages can be used to control the power required for programming.
摘要翻译：一种具有多个存储单元的存储器件，每个存储体具有多个存储器单元，以及一种编程器件中的多个存储器单元的方法，其中偏置电压施加到多个存储器单元的公共源极端子，并且将时变电压施加到要编程的存储单元。在一个实施例中，施加到要编程的存储器单元的栅极的电压是斜坡电压。在第二实施例中，施加到待编程的存储器单元的栅极的电压是增加的阶梯电压。在另一个实施例中，选择施加到公共源极端子的偏置电压和施加到要编程的存储器单元的控制栅极的电压，使得流过被编程的单元的电流减小，并且来自存储器单元的泄漏电流不被编程的基本上被消除。在另一个实施例中，将偏置电压施加到公共源极端子，并将偏置电压施加到公共井电压。施加到控制栅极和源极的电压的组合减少了位线上的负载，以确保VDS不会降低到在编程期间维持热载流子效应所需的水平。偏置电压也可以施加到存储单元的阱，同时公共源极保持在地。编程栅极电压的反馈控制可用于控制编程所需的功率。

2. 发明授权

US5875130A Method for programming flash electrically erasable programmable read-only memory 失效
标题翻译：闪存电可擦除可编程只读存储器的编程方法
公开(公告)号：US5875130A
公开(公告)日：1999-02-23
申请号：US085705
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
IPC分类号： G11C16/10 , G11C16/34 , G11C13/00
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/3404
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括半导体衬底和多个场效应晶体管存储单元，每个具有形成在衬底上的源极，漏极，浮置栅极和控制栅极。控制器控制电源以将操作脉冲施加到单元的漏极，并且在施加操作脉冲时将源施加到单元的衬底偏置电压，所述偏置电压具有被选择为减少或基本上消除的值电池中的漏电流。操作脉冲可以是过高修正脉冲。在这种情况下，在过扫描校正脉冲的持续时间内，向控制栅极施加基本上等于偏置电压的电压。操作脉冲也可以是编程脉冲。在这种情况下，在编程脉冲的持续时间内，将高于偏置电压的电压施加到所选字线的控制栅极。偏置电压优选地在过电压过程校正和编程脉冲期间都被施加，从而降低功率需求并将电池的背景泄漏减小到能够可操作地执行程序，读取和过电压校正操作的电平。

3. 发明授权

US6046932A Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM 有权
标题翻译：电路实现在闪存EEPROM中编程和过擦除校正模式中的位线漏电流
公开(公告)号：US6046932A
公开(公告)日：2000-04-04
申请号：US417273
申请日：1999-10-13
申请人： Colin Bill , Sameer S. Haddad , Jonathan Shi-Chang Su , Vei-Han Chan
发明人： Colin Bill , Sameer S. Haddad , Jonathan Shi-Chang Su , Vei-Han Chan
IPC分类号： G11C16/06 , G11C16/02 , G11C16/30 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C16/12 , G11C16/16
CPC分类号： G11C16/3409 , G11C16/30 , G11C16/3404
摘要： A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.
摘要翻译：一种用于在编程和过擦除校正操作期间淬灭位线泄漏电流的闪存器件的方法和闪存器件。闪存单元被组织成具有每个块具有列和行的I / O块的阵列。公共阵列源连接和地之间连接一组电阻。电阻器阵列由电阻器组成，每组具有编程模式电阻器和APDE模式电阻器。当选择编程或APDE的位线时，数据缓冲区将编程模式电阻器或APDE模式电阻器切换到电路中。选择电阻器的值以将源极处的电压提高到存储器单元的选定阈值电压以上，使得在编程或APDE期间，过擦除的单元将不会向位线提供泄漏电流。

4. 发明授权

US5901090A Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 失效
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US5901090A
公开(公告)日：1999-05-04
申请号：US85552
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Colin S. Bill , Vei-Han Chen
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Colin S. Bill , Vei-Han Chen
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/3409 , G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or "soft programming" pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个具有源极，漏极，浮动栅极和控制栅极的场效应晶体管存储单元，以及用于向单元提供多个电压的电源。控制器控制电源向单元施加至少一个擦除脉冲。然后，将至少一个过度校正或“软编程”脉冲施加到单元，在该单元期间，单元的源极，漏极和控制栅极电压使得过度流过的单元的阈值电压将增加，但是最小擦除的单元将不会被打扰过度校正脉冲从而使阈值电压分布紧密。在过渡期校正脉冲的持续时间内施加衬底偏置电压源，即使在具有低电源电压的应用中，也可以将电池的背景泄漏降低到可以有效执行过电压修正操作的水平。

5. 发明授权

US6157572A Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 失效
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US6157572A
公开(公告)日：2000-12-05
申请号：US85680
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chen , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chen , Colin S. Bill
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase pulse to all wordlines which are not deselected. Then, an erase verify procedure is applied to the cells in sequence. If all cells connected to a wordline pass the erase verify test, the wordline is deselected such that subsequent erase pulses will not be applied to the wordline and possibly cause the cells to become overerased. In one embodiment of the invention, erase verify is performed on all of the cells after an erase pulse is applied. The erase operation is completed when all cells pass erase verify. In another embodiment, erase verify is applied to each cell in sequence, with erase pulses being applied until each current cell passes erase verify. The wordlines can be deselected individually or in groups. The invention results in a tightening of the threshold voltage distribution of the cells.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个浮栅晶体管存储单元，连接到单元的多个字线和用于产生擦除脉冲的电源。控制器控制电源以将擦除脉冲施加到未被取消选择的所有字线。然后，按顺序对单元应用擦除验证程序。如果连接到字线的所有单元都通过擦除验证测试，则字线被取消选择，使得后续的擦除脉冲不会被施加到字线并且可能导致单元变得过高。在本发明的一个实施例中，在施加擦除脉冲之后对所有单元执行擦除验证。当所有单元通过擦除验证时，擦除操作完成。在另一实施例中，按顺序对每个单元施加擦除验证，其中施加擦除脉冲，直到每个当前单元通过擦除验证。字母可以单独或分组取消选择。本发明导致电池的阈值电压分布的紧缩。

6. 发明授权

US6005808A Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices 失效
公开(公告)号：US6005808A
公开(公告)日：1999-12-21
申请号：US993570
申请日：1997-12-18
申请人： Daniel Sobek , Timothy James Thurgate , Scott D. Luning , Vei-Han Chan , Sameer S. Haddad
发明人： Daniel Sobek , Timothy James Thurgate , Scott D. Luning , Vei-Han Chan , Sameer S. Haddad
摘要： A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

7. 发明授权

US06236596B1 Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices 有权
标题翻译：在擦除闪速存储器件期间减少带 - 带和/或雪崩电流的偏置方法和结构
公开(公告)号：US06236596B1
公开(公告)日：2001-05-22
申请号：US09461376
申请日：1999-12-15
申请人： Daniel Sobek , Timothy James Thurgate , Scott D. Luning , Vei-Han Chan , Sameer S. Haddad
发明人： Daniel Sobek , Timothy James Thurgate , Scott D. Luning , Vei-Han Chan , Sameer S. Haddad
IPC分类号： G11C1134
CPC分类号： G11C16/14
摘要： A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.
摘要翻译：提供了一种用于在快速EEPROM存储单元的擦除期间减小带 - 带电流的方法和装置。该装置在衬底上具有背偏压连接，在擦除EEPROM存储单元期间施加偏置电压。在闪存EEPROM存储单元擦除期间将偏置电压施加到反向偏置连接的方法在擦除闪速存储单元期间减少源区和衬底之间的带间电流。这种减少提供了闪存单元的栅极尺寸减小，而不会引起有害的短沟道效应。

8. 发明授权

US06452840B1 Feedback method to optimize electric field during channel erase of flash memory devices 有权
标题翻译：用于优化闪存器件通道擦除期间电场的反馈方法
公开(公告)号：US06452840B1
公开(公告)日：2002-09-17
申请号：US09693649
申请日：2000-10-21
申请人： Ravi S. Sunkavalli , Lee Cleveland , Sameer S. Haddad , Richard Fastow , Tim Thurgate
发明人： Ravi S. Sunkavalli , Lee Cleveland , Sameer S. Haddad , Richard Fastow , Tim Thurgate
IPC分类号： G11C1604
CPC分类号： G11C16/3477 , G11C16/344 , G11C16/3445 , G11C16/3472
摘要： A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the erase vertical electrical field that is to be applied to the array. The vertical electrical field is adjusted by changing the gate voltage, the well voltage or changing both simultaneously.
摘要翻译：一种擦除闪速存储器件的方法，其提高可靠性并减少擦除速度的降低。在擦除阶段或验证阶段期间确定擦除状态，并将信息反馈到调整要应用于阵列的擦除垂直电场的控制器。通过改变栅极电压，井电压或同时改变两者来调节垂直电场。

9. 发明授权

US06188609B1 Ramped or stepped gate channel erase for flash memory application 有权
标题翻译：用于闪存应用的斜坡或步进门控通道擦除
公开(公告)号：US06188609B1
公开(公告)日：2001-02-13
申请号：US09307259
申请日：1999-05-06
申请人： Ravi S. Sunkavalli , Sameer S. Haddad
发明人： Ravi S. Sunkavalli , Sameer S. Haddad
IPC分类号： G11C1606
CPC分类号： G11C16/16
摘要： A method for erasing a flash EEPROM cell by applying a voltage differential between the control gate and the well of the memory cell. The voltage differential can be a ramped or stepped voltage applied to the control gate, a ramped or stepped voltage applied to the well, or a ramped or stepped voltage applied to the control gate and a ramped or stepped voltage applied to the well. The ramped voltages can have a constant slope or the slope can vary. The stepped voltages can be incremented equally or unequally. The voltages applied to the well or to the control gate is ramped or stepped until a selected number of memory cells verify as erased at which time the voltages applied to the well or to the control gate is clamped until the erase procedure is finished.
摘要翻译：一种通过在控制栅极和存储单元的阱之间施加电压差来擦除快闪EEPROM单元的方法。电压差可以是施加到控制栅极的斜坡或阶梯电压，施加到阱的斜坡或阶梯电压，或施加到控制栅极的斜坡或阶梯电压以及施加到阱的斜坡或阶梯电压。斜坡电压可以具有恒定的斜率或斜率可以变化。阶梯电压可以相等或不平等地递增。施加到阱或控制栅极的电压是斜坡或阶梯直到选定数量的存储单元验证为擦除，此时施加到阱或控制栅极的电压被钳位直到擦除过程完成。

10. 发明授权

US06172914B2 Concurrent erase verify scheme for flash memory applications 有权
标题翻译： Flash存储器应用程序的并发擦除验证方案
公开(公告)号：US06172914B2
公开(公告)日：2001-01-09
申请号：US09404078
申请日：1999-09-23
申请人： Sameer S. Haddad , Colin Bill , Michael Van BusKirk
发明人： Sameer S. Haddad , Colin Bill , Michael Van BusKirk
IPC分类号： G11C1604
CPC分类号： G11C16/3472 , G11C16/3468
摘要： A method for sensing the state of erasure of a flash (EEPROM) memory device. In one embodiment, the source voltage during erase is monitored and compared to a value determined during a characterization procedure. In a second embodiment, the rate of change of the source voltage during erase is determined and compared to a value determined during a characterization procedure. The characterization procedure correlates state of erasure with source voltages and slopes of the rate of change of source voltage versus time curve for the memory cells. The determination of the source voltage and the determination of the rate of change of the source voltage and the associated state of erasure allows modification of the erase procedure.
摘要翻译：一种用于检测闪存（EEPROM）存储器件擦除状态的方法。在一个实施例中，监视擦除期间的源电压并将其与在表征过程中确定的值进行比较。在第二实施例中，确定擦除期间的源电压的变化率并将其与表征过程中确定的值进行比较。表征过程将擦除状态与源电压和存储器单元的源电压与时间曲线的变化率的斜率相关联。源电压的确定和源电压的变化率的确定以及相关的擦除状态允许修改擦除过程。

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