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1. 发明申请

US20070025166A1 Program/erase waveshaping control to increase data retention of a memory cell 审中-公开
标题翻译：编程/擦除波形整形控制以增加存储单元的数据保留
公开(公告)号：US20070025166A1
公开(公告)日：2007-02-01
申请号：US11191126
申请日：2005-07-27
申请人： Tzu-Ning Fang , Colin Bill , Wei Cai , David Gaun , Eugen Gershon
发明人： Tzu-Ning Fang , Colin Bill , Wei Cai , David Gaun , Eugen Gershon
IPC分类号： G11C29/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0007 , G11C13/0016 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/32 , G11C2213/71 , G11C2213/77
摘要： System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.
摘要翻译：公开了改进和控制存储单元数据保持的系统和方法。产生特定的脉冲宽度和幅度并将其施加到由至少两个电极制成的存储器单元，该至少两个电极在至少两个电极之间具有可控导电的介质。检测存储器单元中的电流，并将较低的输入脉冲发送到存储单元。下部脉冲的应用控制存储器单元的数据保持，而不会干扰存储单元的最终编程状态。

2. 发明申请

US20080151669A1 USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS 有权
标题翻译：在中继记忆阵列中使用周期性刷新
公开(公告)号：US20080151669A1
公开(公告)日：2008-06-26
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

3. 发明授权

US07072781B1 Architecture for generating adaptive arbitrary waveforms 失效
标题翻译：用于生成自适应任意波形的体系结构
公开(公告)号：US07072781B1
公开(公告)日：2006-07-04
申请号：US10885284
申请日：2004-07-06
申请人： Eugen Gershon , David Gaun , Colin S. Bill , Tzu-Ning Fang
发明人： Eugen Gershon , David Gaun , Colin S. Bill , Tzu-Ning Fang
IPC分类号： G01R31/36
CPC分类号： G01R31/31924 , G01R31/3167 , G01R31/31908 , G11C29/56 , G11C29/56004
摘要： A test system having a feedback loop that facilitates adjusting an output test waveform to a DUT/CUT (Device Under Test/Circuit Under Test) on-the-fly according to changing DUT/CUT parameters. The system includes a tester having an arbitrary waveform generator (AWG) and a data acquisition system (DAS) that monitors the status of the DUT/CUT. The AWG and DAS connect to the DUT/CUT through a feedback loop where the AWG outputs the test waveform to the DUT/CUT, the DAS monitors the DUT/CUT parameters, and the DAS analyzes and communicates changes to the AWG to effect changes in the output waveform, when desired. The AWG builds the output waveform in small slices (or segments) that are assembled together through a process of selection and calibration. The feedback architecture facilitates a number of changes in the output waveform, including a change in the original order of the preassembled slices, and changes in the magnitude/shape of the output waveform.
摘要翻译：具有反馈回路的测试系统，其根据改变的DUT / CUT参数，有助于将DUT / CUT（被测设备/待测电路）的输出测试波形实时调整。该系统包括具有任意波形发生器（AWG）的测试器和监视DUT / CUT的状态的数据采集系统（DAS）。 AWG和DAS通过反馈回路连接到DUT / CUT，AWG将测试波形输出到DUT / CUT，DAS监视DUT / CUT参数，DAS分析并传送AWG的变化，以实现更改输出波形。 AWG通过选择和校准过程组装在一起的小片（或片段）中构建输出波形。反馈架构有助于输出波形的一些变化，包括预先组装的切片的原始顺序的改变以及输出波形的幅度/形状的变化。

4. 发明授权

US07474579B2 Use of periodic refresh in medium retention memory arrays 有权
标题翻译：在介质保留存储器阵列中使用定期更新
公开(公告)号：US07474579B2
公开(公告)日：2009-01-06
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

5. 发明申请

US20100205513A1 SYSTEMS AND METHODS FOR LOCATING ERROR BITS IN ENCODED DATA 有权
标题翻译：用于定位编码数据中的错误位的系统和方法
公开(公告)号：US20100205513A1
公开(公告)日：2010-08-12
申请号：US12368835
申请日：2009-02-10
申请人： Ping Hou , Eugen Gershon
发明人： Ping Hou , Eugen Gershon
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： G06F11/1008 , H03M13/152 , H03M13/1525 , H03M13/1545 , H03M13/6561
摘要： Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.
摘要翻译：公开了用于识别编码数据中的错误位的系统和方法。作为识别错误位的一部分，访问从数据源提供并且包括数据和奇偶校验部分的编码数据。基于编码数据，计算综合征，并且基于所计算的综合征，确定方程式。确定等式的根，并且基于确定的等式的根，识别一个或多个错误位。使用呈现根的二进制表示的电路来识别错误位。错误位根据识别的错误位进行校正。

6. 发明授权

US06175316B1 Bin-to-bin differential encoding apparatus and method for a discrete multi-tone transmission system 失效
标题翻译：用于离散多音调传输系统的Bin-to-bin差分编码装置和方法
公开(公告)号：US06175316B1
公开(公告)日：2001-01-16
申请号：US09287263
申请日：1999-04-07
申请人： Maged F. Barsoum , Hungming Chang , Eugen Gershon , Chien-Meen Hwang , Muoi V. Huynh
发明人： Maged F. Barsoum , Hungming Chang , Eugen Gershon , Chien-Meen Hwang , Muoi V. Huynh
IPC分类号： H03M510
CPC分类号： H04L27/2602 , H03M5/10
摘要： A discrete multi-tone communication system employing bin-to-bin differential encoding of data frames to be transmitted within the communication system. The bin-to-bin differential encoding utilizes the phase angle of previously encoded data to encode the current data relative to that phase angle. Hence, only a single reference tone is required to encode a first portion of the data frame into a discrete tone, and then the remaining data portions of the data frame are each subsequently encoded into discrete tones with reference to the phase angle of data already encoded into a discrete tone. Thus, to achieve decoding, a decoding device only requires the reference tone to begin decoding the discrete tones to the correct phase angle for an accurate reproduction of the original data frame.
摘要翻译：一种离散的多音通信系统，采用在通信系统内发送的数据帧的二进制差分编码。 bin到bin的差分编码利用先前编码的数据的相位角来相对于该相位角对当前数据进行编码。因此，仅需要单个参考音来将数据帧的第一部分编码成离散音调，然后参考已经编码的数据的相位角，数据帧的剩余数据部分随后被编码成离散音调变成离散的音调。因此，为了实现解码，解码装置仅需要参考音开始将离散音调解码为正确的相位角，以准确再现原始数据帧。

7. 发明授权

US5828733A Method and arrangement for increasing data transmisssion rate over telephone cable 失效
标题翻译：通过电话线增加数据传输速率的方法和布置
公开(公告)号：US5828733A
公开(公告)日：1998-10-27
申请号：US416129
申请日：1995-04-03
申请人： David M. Barton , Eugen Gershon , Muoi Huynh
发明人： David M. Barton , Eugen Gershon , Muoi Huynh
IPC分类号： H04L5/20 , H04M11/00 , H04B1/38
CPC分类号： H04L5/20
摘要： A method and arrangement for transferring data between nodes over a telephone cable that couples the nodes provides a dual configuration node transmitter, and a dual configuration node receiver. The dual configuration transmitter has a first transmitter circuit that transmits data over a first configuration of the telephone cable and a second transmitter that simultaneously transmits other data over a second configuration of the telephone cable. The dual configuration receiver is coupled to the telephone cable and has a first receiver circuit that selects the data transmitted by the first transmitter circuit and rejects the data transmitted by the second transmitter circuit, and a second receiver circuit that selects the data transmitted by the second transmitter circuit and rejects the data transmitted by the first transmitter circuit. The transmitting of data over two configurations of the same cable allows data to be transmitted twice as fast as over the same cable set up for transmission in a single configuration. Alternatively, in an Ethernet application, one configuration may carry the data while the other configuration simultaneously carries activity information.
摘要翻译：用于通过耦合节点的电话电缆在节点之间传送数据的方法和装置提供双配置节点发射机和双配置节点接收机。双重配置发射机具有通过电话线的第一配置发送数据的第一发射机电路和通过电话线的第二配置同时发射其他数据的第二发射机。双重配置接收器耦合到电话电缆，并且具有第一接收器电路，其选择由第一发射机电路发送的数据并且拒绝由第二发射机电路发送的数据;以及第二接收机电路，其选择由第二发射机发送的数据发射机电路并拒绝第一发射机电路传输的数据。通过同一电缆的两种配置的数据传输，允许将数据传输速度快于在单一配置中传输的相同电缆的两倍。或者，在以太网应用中，一个配置可以携带数据，而另一个配置同时携带活动信息。

8. 发明授权

US5604464A Cascode operational amplifier with multiple input stage 失效
标题翻译：具有多输入级的串联运算放大器
公开(公告)号：US5604464A
公开(公告)日：1997-02-18
申请号：US499315
申请日：1995-07-07
申请人： Chien-Meen Hwang , Eugen Gershon
发明人： Chien-Meen Hwang , Eugen Gershon
IPC分类号： H03F3/45
CPC分类号： H03F3/4521 , H03F3/45188 , H03F3/45192 , H03F3/4565 , H03F3/45654 , H03F2203/45578
摘要： Disclosed herein is a cascode operational amplifier design with multiple input stages, and methods of operating the same, resulting in enhanced output gain and unity gain bandwidth operational amplifiers. The cascode operational amplifier comprises a differential input block which receives a differential input having a first differential input stage and a second differential input stage. A cascode block is coupled to the differential input block and provides a differential output for the operational amplifier. A common mode feedback block coupled to the second differential input stage of the differential input block and the differential output of the cascode block stabilizes a DC output level for the differential output. A load block is coupled to the differential output of the cascode block and applies a resistive load to the differential output in response to a differential input signal applied to the differential input block.
摘要翻译：这里公开了具有多个输入级的共源共栅运算放大器设计及其操作方法，导致增强的输出增益和单位增益带宽运算放大器。共源共栅运算放大器包括差分输入块，其接收具有第一差分输入级和第二差分输入级的差分输入。共源共栅块耦合到差分输入块，并为运算放大器提供差分输出。耦合到差分输入块的第二差分输入级的共模反馈块和共源共栅组的差分输出稳定用于差分输出的DC输出电平。负载块耦合到共源共栅块的差分输出，并响应于施加到差分输入块的差分输入信号，向差分输出施加电阻性负载。

9. 发明授权

US08255777B2 Systems and methods for locating error bits in encoded data 有权
标题翻译：用于定位编码数据中错误位的系统和方法
公开(公告)号：US08255777B2
公开(公告)日：2012-08-28
申请号：US12368835
申请日：2009-02-10
申请人： Ping Hou , Eugen Gershon
发明人： Ping Hou , Eugen Gershon
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , H03M13/152 , H03M13/1525 , H03M13/1545 , H03M13/6561
摘要： Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.
摘要翻译：公开了用于识别编码数据中的错误位的系统和方法。作为识别错误位的一部分，访问从数据源提供并且包括数据和奇偶校验部分的编码数据。基于编码数据，计算综合征，并且基于所计算的综合征，确定方程式。确定等式的根，并且基于确定的等式的根，识别一个或多个错误位。使用呈现根的二进制表示的电路来识别错误位。错误位根据识别的错误位进行校正。

10. 发明申请

US20080266945A1 ADAPTIVE DETECTION OF THRESHOLD LEVELS IN MEMORY 失效
标题翻译：自适应检测记忆中的阈值水平
公开(公告)号：US20080266945A1
公开(公告)日：2008-10-30
申请号：US11742371
申请日：2007-04-30
申请人： Ping Hou , Eugen Gershon , Michael A. Van Buskirk
发明人： Ping Hou , Eugen Gershon , Michael A. Van Buskirk
IPC分类号： G11C11/34
CPC分类号： G11C11/5642
摘要： Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.
摘要翻译：介绍了便于从存储器访问数据的系统，方法和/或设备。可以采用自适应检测部件来减少或最小化检测误差，并且在读取操作期间区分存储在存储器单元中的信息。解码器组件可以包括自适应检测组件，其可以采用自适应林德 - 布佐灰色（LBG）算法。解码器组件可以在读取操作期间从存储器位置接收与当前级别相关联的信息，并且可以分析和处理这样的信息。自适应检测组件可以接收经处理的信息，并且与其他信息一起可以使用迭代LBG算法来处理这样的信息，直到确定重建级别和对应的阈值级别为止。可以将这样的重建级别和/或阈值级别与与从存储器位置读取的信息相关联的值进行比较，以确定存储器位置中的数据的数据值。

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