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1. 发明授权

US07227768B2 Power interconnect structure for balanced bitline capacitance in a memory array 有权
标题翻译：用于存储器阵列中平衡位线电容的功率互连结构
公开(公告)号：US07227768B2
公开(公告)日：2007-06-05
申请号：US11173930
申请日：2005-07-01
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C5/06
CPC分类号： H01L23/5286 , H01L23/5222 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor die. The semiconductor die further includes an interconnect structure situated over the memory core array, where the interconnect structure is situated in a second interconnect metal layer in the semiconductor die and situated over each of the bitlines. The interconnect structure can include at least one interconnect line, which can form an angle with respect to the bitlines that can be greater than 0.0 degrees and less than or equal to 90.0 degrees. The interconnect structure can form one of a number of capacitances with each of the bitlines, where each of the capacitances can be substantially equal in value to each other of the capacitances.
摘要翻译：根据一个示例性实施例，半导体管芯包括位于衬底上的存储器芯阵列，其中存储器芯阵列包括多个位线，其中位线可以位于半导体管芯中的第一互连金属层中。半导体管芯还包括位于存储器芯阵列上方的互连结构，其中互连结构位于半导体管芯中的第二互连金属层中并且位于每个位线上。互连结构可以包括至少一个互连线，其可以相对于位线形成可以大于0.0度且小于或等于90.0度的角度。互连结构可以形成与每个位线的多个电容中的一个，其中每个电容可以在电容中彼此的值基本相等。

2. 发明申请

US20060023539A1 Semiconductor device and method of generating sense signal 有权
标题翻译：半导体器件和产生感测信号的方法
公开(公告)号：US20060023539A1
公开(公告)日：2006-02-02
申请号：US11194007
申请日：2005-07-29
申请人： Tsutomu Nakai , Takao Akaogi , Kazuhide Kurosaki
发明人： Tsutomu Nakai , Takao Akaogi , Kazuhide Kurosaki
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/067 , G11C11/5642 , G11C16/28 , G11C2211/5645
摘要： A semiconductor device includes a first cascode circuit having a first current mirror amplifying a reference current flowing through a data line of a reference cell, and a second current mirror generating a first potential from an amplified reference current; and a second cascode circuit having a third current mirror amplifying a core current flowing through a data line of a core cell, and a transistor receiving a gate voltage corresponding to the amplified reference current and generating a second potential based on a difference between an amplified core cell current and the amplified reference current. Since the second potential is generated by the difference between the core cell current and the reference cell current, the second potential swings in the full range of the ground power supply voltage to the ground potential, and the range of the amplitude of the power supply voltage can be efficiently utilized. Sensing is enabled for a fine current margin.
摘要翻译：半导体器件包括第一共源共栅电路，其具有放大流过参考单元的数据线的参考电流的第一电流镜和从放大的参考电流产生第一电位的第二电流镜; 以及第二共源共栅电路，其具有放大流过芯电池的数据线的芯电流的第三电流镜，以及接收与放大的参考电流相对应的栅极电压的晶体管，并且基于放大芯之间的差产生第二电位电池电流和放大参考电流。由于第二电位是由芯电池电流和参考电池电流之间的差产生的，所以第二电位在接地电源电压的全范围内摆动到接地电位，电源电压幅度的范围可以有效利用。感应功能可用于精细的电流裕度。

3. 发明授权

US06611464B2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics 失效
公开(公告)号：US06611464B2
公开(公告)日：2003-08-26
申请号：US10265233
申请日：2002-10-07
申请人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita , Shouichi Kawamura
发明人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita , Shouichi Kawamura
IPC分类号： G11C1604
CPC分类号： G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

4. 发明授权

US06507527B1 Memory line discharge before sensing 有权
标题翻译：感应前存储线放电
公开(公告)号：US06507527B1
公开(公告)日：2003-01-14
申请号：US09698614
申请日：2000-10-27
申请人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
发明人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/12
摘要： A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.
摘要翻译：一种通过将数据线从高于期望电压电平的电压电平放电到大约期望的电压电平，在数据线在低功率存储器件中被感测之前将数据线充电到期望的电压电平的方法。通过使用N型晶体管将数据线放电至期望的电压电平，可以用更便宜的组件更快地达到电压电平。

5. 发明授权

US06414874B2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics 失效
公开(公告)号：US06414874B2
公开(公告)日：2002-07-02
申请号：US09832916
申请日：2001-04-12
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C1604
CPC分类号： G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

6. 发明授权

US06359808B1 Low voltage read cascode for 2V/3V and different bank combinations without metal options for a simultaneous operation flash memory device 有权
标题翻译：低电压读取共源共栅，适用于2V / 3V和不同的组合组合，无需金属选项，可同时操作闪存器件
公开(公告)号：US06359808B1
公开(公告)日：2002-03-19
申请号：US09421985
申请日：1999-10-19
申请人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
发明人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
IPC分类号： G11C1606
CPC分类号： G11C16/26
摘要： A pre-amplifier portion of a sense amplifier for a dual bank architecture simultaneous operation flash memory device is provided. The sense pre-amplifier circuit includes two inverting amplifiers, the second inverting amplifier providing a feedback loop for the first inverting amplifier. In addition, special “kicker” circuitry raises the sense pre-amplifier's input signal line to its operating level. The combination of inverting amplifiers, feedback loop and level raising circuitry is configured to provide higher bandwidths for the sense pre-amplifier to accommodate low capacitive loading resulting from a small memory bank. The combination is also configured to provide faster raising of the input signal line to operating level to accommodate high capacitive loading resulting from a large memory bank. The combination is also configured to provide increased signal margins at the output of the sense pre-amplifier.
摘要翻译：提供了用于双存储体架构同时操作闪速存储器件的读出放大器的前置放大器部分。感测预放大器电路包括两个反相放大器，第二反相放大器为第一反相放大器提供反馈回路。另外，特殊的“咔icker”电路将感应前置放大器的输入信号线提升到其工作电平。反相放大器，反馈回路和电平提升电路的组合被配置为为感测前置放大器提供更高的带宽以适应由小存储器组成的低容性负载。该组合还被配置为将输入信号线更快地提升到操作电平以适应由大存储器组造成的高容性负载。该组合还被配置为在感测前置放大器的输出处提供增加的信号余量。

7. 发明授权

US06240040B1 Multiple bank simultaneous operation for a flash memory 有权
标题翻译：多存储银行同时操作闪存
公开(公告)号：US06240040B1
公开(公告)日：2001-05-29
申请号：US09526239
申请日：2000-03-15
申请人： Takao Akaogi , Lee Edward Cleveland , Kendra Nguyen
发明人： Takao Akaogi , Lee Edward Cleveland , Kendra Nguyen
IPC分类号： G11C800
CPC分类号： G11C16/26 , G11C16/08 , G11C16/10 , G11C2216/22
摘要： An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N-1 banks. The address buffering and decoding architecture includes a control logic circuit, an address selection circuit located at each of the N banks, and address buffer circuitry. The control logic circuit is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation. Each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals. The address buffer circuitry is used to simultaneously provide a write address and a read address in order to access core memory cells. Respective first portions of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals. Respective second portions of the write and read addresses are provided to the respective address selection circuit.
摘要翻译：描述了用于多组（或N组）同时操作闪速存储器的地址缓冲和解码架构。对于在N个存储体的一个存储体中的读取操作的持续时间，只能对其他N-1个存储体中的任一个进行写入操作。对于在N个存储体的一个存储体中的写入操作的持续时间，只能对其他N-1个存储体中的任一个进行读取操作。地址缓冲和解码架构包括控制逻辑电路，位于N个存储体中的每一个的地址选择电路和地址缓冲器电路。控制逻辑电路用于产生N个读取选择信号以选择用于读取操作的N个存储体中的一个存储单元和N个写入选择信号，以便为写入操作选择N个存储体的另一个存储体。每个地址选择电路被配置为从控制逻辑电路接收N个读选择信号中的相应一个和N个写入选择信号中的相应一个。地址缓冲器电路用于同时提供写入地址和读取地址以便访问核心存储器单元。将写入和读取地址的各个第一部分提供给控制逻辑电路以产生相应的N个读取选择信号和N个写入选择信号。将写入和读取地址的相应第二部分提供给相应的地址选择电路。

8. 发明授权

US06205084B1 Burst mode flash memory 有权
标题翻译：突发模式闪存
公开(公告)号：US06205084B1
公开(公告)日：2001-03-20
申请号：US09467758
申请日：1999-12-20
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C300
CPC分类号： G11C7/225 , G11C7/1051 , G11C7/106 , G11C7/22 , G11C7/222 , G11C16/26 , G11C16/32
摘要： A clock generator circuit in response to an external output enable signal generates an internal clock signal that is delayed to increase the reliability of the data outputted from the flash memory. A clock trigger generator circuit by decoding address signals generates an internal clock signal to reduce the latency time of the output of data with respect to the external clock signal. A bypass signal is provided to disable the clock trigger generator circuit. An output circuit provides a bypass data path to additionally reduce the latency time of the outputting of data for a burst mode flash memory. A decoder counter selector circuit provides a “look-ahead” address decoding scheme to reduce the time needed to output data.
摘要翻译：响应于外部输出使能信号的时钟发生器电路产生延迟的内部时钟信号，以增加从闪速存储器输出的数据的可靠性。通过解码地址信号的时钟触发发生器电路产生内部时钟信号，以减少数据相对于外部时钟信号输出的等待时间。提供旁路信号来禁止时钟触发发生器电路。输出电路提供旁路数据路径以额外地减少突发模式闪速存储器输出数据的等待时间。解码器计数器选择器电路提供“先行”地址解码方案，以减少输出数据所需的时间。

9. 发明授权

US6111787A Address transistion detect timing architecture for a simultaneous operation flash memory device 有权
标题翻译：地址转移检测定时架构，用于同时运行的闪存设备
公开(公告)号：US6111787A
公开(公告)日：2000-08-29
申请号：US421776
申请日：1999-10-19
申请人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
发明人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
IPC分类号： G11C8/12 , G11C8/18 , G11C16/32 , G11C16/04 , G11C8/00
CPC分类号： G11C16/32 , G11C8/12 , G11C8/18
摘要： An address transition signal generator for a dual bank flash memory device is disclosed. The generator includes signal transition detectors which monitor control signals of the device for transitions in their logical values. Upon detection of a signal transition, the transition detectors send a signal across equidistant signal paths to bank address transition detect signal generator circuits. This results in simultaneous generation of the address transition detect signal from each of the bank address transition detect signal generator circuits.
摘要翻译：公开了一种用于双银行闪存设备的地址转换信号发生器。发生器包括信号转换检测器，其监视器件的控制信号用于其逻辑值中的转换。在检测到信号转换时，转换检测器通过等距信号路径向bank地址转换检测信号发生器电路发送信号。这导致从每个存储体地址转换检测信号发生器电路同时生成地址转换检测信号。

10. 发明授权

US5835408A Flash-erasable semiconductor memory device having an improved reliability 失效
公开(公告)号：US5835408A
公开(公告)日：1998-11-10
申请号：US985714
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

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