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1. 发明授权

US07010736B1 Address sequencer within BIST (Built-in-Self-Test) system 有权
标题翻译： BIST（内置自检）系统中的地址排序器
公开(公告)号：US07010736B1
公开(公告)日：2006-03-07
申请号：US10200518
申请日：2002-07-22
申请人： Boon Tang Teh , Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill , Joseph Kucera , Weng Fook Lee , Darlene G. Hamilton
发明人： Boon Tang Teh , Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill , Joseph Kucera , Weng Fook Lee , Darlene G. Hamilton
IPC分类号： G01R31/28
CPC分类号： G11C29/36 , G11C15/00 , G11C16/04 , G11C29/12005 , G11C29/16 , G11C29/18 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/52 , G11C29/76 , G11C2029/1208 , G11C2029/3602
摘要： An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.
摘要翻译：在其上制造闪存单元的半导体衬底上制造地址序列器，用于在快闪存储器单元的BIST（内置自测试）期间对闪存单元进行排序。地址排序器包括在半导体衬底上制造的地址定序器控制逻辑和地址序列器缓冲器。地址顺序器缓冲器产生指示闪存单元的地址的多个位。地址定序器控制逻辑控制缓冲器以通过针对多个BIST模式中的每一个的相应的位模式序列进行排序。

2. 发明授权

US07028240B1 Diagnostic mode for testing functionality of BIST (built-in-self-test) back-end state machine 有权
标题翻译：用于测试BIST（内置自检）后端状态机的功能的诊断模式
公开(公告)号：US07028240B1
公开(公告)日：2006-04-11
申请号：US10200526
申请日：2002-07-22
申请人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill
发明人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill
IPC分类号： G01R3/28
CPC分类号： G11C29/02 , G11C16/04 , G11C29/16
摘要： In a method and system for diagnosing a back-end state machine used for testing flash memory cells fabricated on a semiconductor substrate, a signal selector and a diagnostic matching logic are fabricated on the semiconductor substrate. The diagnostic matching logic sets a generated match output to a pass or fail state depending on control variables from the back-end state machine. The signal selector selects the generated match output to be used in a verify step of a BIST (built-in-self-test) mode, if a diagnostic mode is invoked. The back-end state machine performs a plurality of BIST modes with the generated match output, for testing the functionality of the back-end state machine.
摘要翻译：在用于诊断用于测试在半导体衬底上制造的闪存单元的后端状态机的方法和系统中，在半导体衬底上制造信号选择器和诊断匹配逻辑。诊断匹配逻辑根据后端状态机的控制变量将生成的匹配输出设置为通过或失败状态。如果调用诊断模式，则信号选择器选择要在BIST（内置自检）模式的验证步骤中使用的生成的匹配输出。后端状态机利用生成的匹配输出执行多个BIST模式，用于测试后端状态机的功能。

3. 发明授权

US06631086B1 On-chip repair of defective address of core flash memory cells 有权
标题翻译：核心闪存单元故障地址的片上修复
公开(公告)号：US06631086B1
公开(公告)日：2003-10-07
申请号：US10200544
申请日：2002-07-22
申请人： Colin Bill , Ken Cheong Cheah , Edward V. Bautista, Jr. , Azrul Halim , Darlene G. Hamilton
发明人： Colin Bill , Ken Cheong Cheah , Edward V. Bautista, Jr. , Azrul Halim , Darlene G. Hamilton
IPC分类号： G11C1606
CPC分类号： G11C29/72 , G11C15/00 , G11C16/04 , G11C29/16 , G11C29/44 , G11C29/48
摘要： In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.
摘要翻译：在用于修复在半导体衬底上制造的有缺陷的闪速存储器单元的方法和系统中，在半导体衬底上制造修复控制器和多个电压源。修理控制器控制电压源以将编程电压施加在JUICE状态的相应CAM（内容可寻址存储器）闪存单元上，以用闪存单元的相应冗余元件代替有缺陷的闪存单元。此外，如果没有闪存单元的冗余元件可用或者有缺陷的闪速存储器单元已经被修复，则在半导体衬底上制造FAILREP逻辑用于进入HANG状态。

4. 发明授权

US06973003B1 Memory device and method 有权
标题翻译：内存设备和方法
公开(公告)号：US06973003B1
公开(公告)日：2005-12-06
申请号：US10677073
申请日：2003-10-01
申请人： Syahrizal Salleh , Edward V. Bautista, Jr. , Ken Cheong Cheah
发明人： Syahrizal Salleh , Edward V. Bautista, Jr. , Ken Cheong Cheah
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40622 , G11C11/406
摘要： A memory device and a method for refreshing the memory device. The memory device includes a memory cell capable of storing two bits of data. One bit is referred to as the normal data bit and the other bit is referred to as the complementary data bit. Each memory cell has an associated dynamic reference cell. The normal data is refreshed by latching refresh data into a data latch and ORing the latched data with input data. The refresh data is written to the corresponding memory location. The data for the complementary data bit is refreshed by latching complementary data bit refresh data into the complementary data latches and writing to the memory cell. The normal and complementary data bits are refreshed before each read operation.
摘要翻译：一种用于刷新存储器件的存储器件和方法。存储器件包括能够存储两位数据的存储器单元。一位被称为正常数据位，另一位称为互补数据位。每个存储单元具有相关联的动态参考单元。正常数据通过将刷新数据锁存到数据锁存器中并将锁存数据与输入数据进行OR运算来刷新。刷新数据被写入相应的存储单元。通过将互补数据位刷新数据锁存到互补数据锁存器中并写入存储单元来刷新补充数据位的数据。正常和互补的数据位在每次读取操作之前刷新。

5. 发明授权

US06980473B1 Memory device and method 有权
标题翻译：内存设备和方法
公开(公告)号：US06980473B1
公开(公告)日：2005-12-27
申请号：US10677031
申请日：2003-10-01
申请人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Chi-Mun Ho
发明人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Chi-Mun Ho
IPC分类号： G11C16/04 , G11C16/12 , G11C16/30 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/12 , G11C16/30 , G11C16/3454 , G11C29/021 , G11C29/028
摘要： A memory device and a method for compensating for a load current in the memory device. The memory device includes a plurality of I/O buffers where each I/O buffer includes an I/O write-buffer driver circuit. The I/O write-buffer driver circuit is coupled to a load current compensation circuit. Although each I/O buffer includes an I/O write-buffer circuit, a single load current compensation circuit may be coupled to several I/O write-buffer driver circuits. The load current compensation circuit generates a load compensation current for each I/O buffer circuit that is not being programmed. The load compensation current increases the load current so that a drain-side programming voltage (VPROG) drives a substantially constant load current, wherein the drain-side programming voltage is substantially independent of the number of bits being programmed.
摘要翻译：一种用于补偿存储器件中的负载电流的存储器件和方法。存储器件包括多个I / O缓冲器，其中每个I / O缓冲器包括I / O写缓冲器驱动电路。 I / O写缓冲器驱动电路耦合到负载电流补偿电路。尽管每个I / O缓冲器都包含一个I / O写缓冲电路，但单个负载电流补偿电路可以耦合到多个I / O写缓冲器驱动电路。负载电流补偿电路为未编程的每个I / O缓冲电路产生负载补偿电流。负载补偿电流增加负载电流，使得漏极侧编程电压（VPROG）驱动基本恒定的负载电流，其中漏极侧编程电压基本上与被编程的位数无关。

6. 发明授权

US06970368B1 CAM (content addressable memory) cells as part of core array in flash memory device 有权
标题翻译： CAM（内容可寻址存储器）单元作为闪存设备中的核心阵列的一部分
公开(公告)号：US06970368B1
公开(公告)日：2005-11-29
申请号：US10650049
申请日：2003-08-26
申请人： Edward V. Bautista, Jr. , Ken Cheong Cheah
发明人： Edward V. Bautista, Jr. , Ken Cheong Cheah
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/046
摘要： In a method and system for providing a CAM (content addressable memory) cell of a flash memory device, a respective core flash memory cell to be used as the CAM cell is fabricated as part of a core array of the flash memory device. In addition, the respective core flash memory cell is accessed from the core array as the CAM cell for a CAM function within the flash memory device. Components used for supporting operation of the core array are also used for accessing the core flash memory cells of the additional sector for such CAM functionality. Thus, CAM functionality is provided with a minimized number of components and with minimized area of the die of the flash memory device. In addition, because the CAM cells are implemented as core flash memory cells of the core array, the CAM cells may reliably undergo more numerous programming and erasing cycles.
摘要翻译：在用于提供闪速存储器件的CAM（内容可寻址存储器）单元的方法和系统中，将要用作CAM单元的相应核心闪速存储器单元制造为闪速存储器件的核心阵列的一部分。此外，各个核心闪存单元从核心阵列作为用于CAM存储器件内的CAM功能的CAM单元访问。用于支持核心阵列操作的组件也用于访问用于这种CAM功能的附加扇区的核心闪存单元。因此，CAM功能被提供有最少数量的部件并且具有闪存器件的管芯的最小面积。另外，由于CAM单元被实现为核心阵列的核心闪存单元，因此CAM单元可以可靠地进行更多的编程和擦除周期。

7. 发明授权

US06665214B1 On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode 有权
标题翻译：片内擦除脉冲计数器，用于高效擦除验证BIST（内置自检）模式
公开(公告)号：US06665214B1
公开(公告)日：2003-12-16
申请号：US10200330
申请日：2002-07-22
申请人： Ken Cheong Cheah , Edward V. Bautista, Jr. , Weng Fook Lee , Boon Tang Teh
发明人： Ken Cheong Cheah , Edward V. Bautista, Jr. , Weng Fook Lee , Boon Tang Teh
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/02 , G11C29/44 , G11C29/48 , G11C29/50 , G11C2029/5002
摘要： In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.
摘要翻译：在用于监视施加在制造在半导体衬底上的快闪存储器单元的扇区上的擦除脉冲的方法和系统中，在半导体衬底上制造脉冲计数器和脉冲计数器控制器。脉冲计数器控制器输入最大数量，并且如果在擦除验证期间扇区的闪速存储单元不通过小于刷新扇区上最大擦除脉冲数的擦除验证，则输出扇区失败的指示BIST（Built- 自检）模式。在一个示例中，最大数量是需要施加在扇区上的擦除脉冲的对角线总数的百分比，直到扇区的对角线位置处的每个闪存单元通过擦除验证。

8. 发明授权

US06771093B1 Implementing reference current measurement mode within reference array programming mode or reference array erase mode in a semiconductor 失效
标题翻译：在半导体的参考阵列编程模式或参考阵列擦除模式下实现参考电流测量模式
公开(公告)号：US06771093B1
公开(公告)日：2004-08-03
申请号：US10254381
申请日：2002-09-25
申请人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Weng Fook Lee
发明人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Weng Fook Lee
IPC分类号： H03K1900
CPC分类号： G01R31/318516 , G01R31/3004
摘要： A method of implementing a reference current measurement mode within a reference array programming mode or a reference array erase mode in a semiconductor chip is disclosed. This implementation leads to significant reduction in testing time for the semiconductor chip, increasing production volume and revenues.
摘要翻译：公开了一种在半导体芯片中的参考阵列编程模式或参考阵列擦除模式中实现参考电流测量模式的方法。这种实现导致半导体芯片的测试时间大大减少，生产量和收入增加。

9. 发明授权

US06707718B1 Generation of margining voltage on-chip during testing CAM portion of flash memory device 失效
标题翻译：在闪速存储器件的测试CAM部分期间片上产生裕度电压
公开(公告)号：US06707718B1
公开(公告)日：2004-03-16
申请号：US10200539
申请日：2002-07-22
申请人： Azrul Halim , Colin Bill , Ken Cheong Cheah , Syahrizal Salleh
发明人： Azrul Halim , Colin Bill , Ken Cheong Cheah , Syahrizal Salleh
IPC分类号： G11C1606
CPC分类号： G11C29/44 , G11C16/04 , G11C29/16 , G11C29/48
摘要： For generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with a voltage generator fabricated on the semiconductor wafer. A low voltage source is provided from a node coupled to the voltage generator fabricated on the semiconductor wafer. For example, the voltage generator for providing the high voltage source includes a voltage regulator and a charge pump fabricated on the semiconductor wafer, and the low voltage source is the ground node. In addition, a first transistor is coupled to the high voltage source, and a second transistor is coupled to the low voltage source. A first resistor is coupled between the first transistor and an output node, and a second resistor coupled between the second transistor and the output node. The margining voltage is generated at the output node. The first resistor and the second resistor form a resistive voltage divider at the output node between the high voltage source and the low voltage source when the first transistor and the second transistor are turned on. A logic circuit turns on the first transistor and the second transistor when a first set of control signals indicate that program margining of the CAM cell during a BIST (built-in-self-test) mode is invoked. The first transistor, the second transistor, the first resistor, the second resistor, and the logic circuit are fabricated on the semiconductor wafer. In another embodiment of the present invention, the logic circuit turns off the first transistor and turns on the second transistor such that the output node discharges to a voltage of the low voltage source for erase margining of the CAM cell.
摘要翻译：为了产生用于偏置制造在半导体晶片上的闪存器件的CAM（内容可寻址存储器）单元的栅极的裕度电压，高电压源设置有制造在半导体晶片上的电压发生器。从耦合到制造在半导体晶片上的电压发生器的节点提供低电压源。例如，用于提供高电压源的电压发生器包括在半导体晶片上制造的电压调节器和电荷泵，而低电压源是接地节点。此外，第一晶体管耦合到高电压源，第二晶体管耦合到低电压源。第一电阻器耦合在第一晶体管和输出节点之间，第二电阻耦合在第二晶体管和输出节点之间。在输出节点产生裕度电压。当第一晶体管和第二晶体管导通时，第一电阻器和第二电阻器在高电压源和低电压源之间的输出节点处形成电阻分压器。当第一组控制信号指示在BIST（内置自测试）模式期间CAM单元的编程余量被调用时，逻辑电路接通第一晶体管和第二晶体管。在半导体晶片上制造第一晶体管，第二晶体管，第一电阻器，第二电阻器和逻辑电路。在本发明的另一个实施例中，逻辑电路关闭第一晶体管并导通第二晶体管，使得输出节点放电到低电压源的电压以消除CAM单元的擦除裕度。

10. 发明授权

US07158442B1 Flexible latency in flash memory 有权
标题翻译：闪存中的灵活延迟
公开(公告)号：US07158442B1
公开(公告)日：2007-01-02
申请号：US11135231
申请日：2005-05-23
申请人： Jih Hong Beh , Ken Cheong Cheah
发明人： Jih Hong Beh , Ken Cheong Cheah
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C16/26
摘要： A method of reading data in and outputting data from a memory structure includes a buffer. In the present method, first read operation is undertaken to read a first set of data in the memory structure and provide data of the first set of data to the buffer, using an output clock. A first output operation is undertaken providing data read in the first read operation from the buffer, and a second read operation is undertaken to read a second set of data in the memory structure and provide data of the second set of data to the buffer, using the output clock. A second output operation is undertaken providing data read in the second read operation from the buffer. In the event that the completion of the first output operation would occur prior to the completion of the provision of the data of the second set of data to the buffer, a flexible time delay approach is undertaken so that, between the completion of the first output operation and the beginning of the second output operation, the minimum number of latencies are added as needed to insure that the provision of the data of the second set of data to the buffer is completed prior to the initiation of the second output operation.
摘要翻译：从存储器结构读取数据并从存储器结构输出数据的方法包括缓冲器。在本方法中，进行第一读取操作以读取存储器结构中的第一组数据，并使用输出时钟向缓冲器提供第一组数据的数据。进行第一输出操作，从缓冲器提供在第一读取操作中读取的数据，并进行第二读取操作以读取存储器结构中的第二组数据，并将第二组数据的数据提供给缓冲器，使用输出时钟。进行第二输出操作，从缓冲器提供在第二读取操作中读取的数据。在完成向缓冲器提供第二组数据的数据之前发生第一输出操作的完成的情况下，进行灵活的时间延迟方法，使得在完成第一输出之间操作和第二输出操作的开始，根据需要添加最小延迟数，以确保在第二输出操作开始之前向缓冲器提供第二组数据的数据。

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