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1. 发明授权

US06420267B1 Method for forming an integrated barrier/plug for a stacked capacitor 有权
标题翻译：用于形成叠层电容器的集成屏障/插头的方法
公开(公告)号：US06420267B1
公开(公告)日：2002-07-16
申请号：US09551757
申请日：2000-04-18
申请人： Chenting Lin , Ronald J. Schutz , Andreas Knorr , Keith Wong , Hua Shen , Jenny Lian
发明人： Chenting Lin , Ronald J. Schutz , Andreas Knorr , Keith Wong , Hua Shen , Jenny Lian
IPC分类号： H01L2100
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.
摘要翻译：提供了一种形成用于层叠电容器的集成屏障/触点的方法，其导致所有权成本降低以及名义上比常规结构厚几倍的屏障。与常规装置相比，所得结构导致接触插头电阻降低。

2. 发明授权

US06339007B1 Capacitor stack structure and method of fabricating description 失效
标题翻译：电容器堆叠结构及其制造方法
公开(公告)号：US06339007B1
公开(公告)日：2002-01-15
申请号：US09562556
申请日：2000-05-02
申请人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
发明人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
IPC分类号： H01L2120
CPC分类号： H01L28/75 , H01L28/55 , H01L28/60
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.
摘要翻译：一种电容器结构，其包括顶部铂电极和在电极的侧壁上具有绝缘体的底部电极，并且其中底部电极从沉积相对于绝缘体在其侧壁上凹进的第一电极部分并且沉积第二绝缘体提供部分。

3. 发明授权

US06365328B1 Semiconductor structure and manufacturing method 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06365328B1
公开(公告)日：2002-04-02
申请号：US09522883
申请日：2000-03-10
申请人： Hua Shen , David Kotecki , Satish Athavale , Jenny Lian , Laertis Economikos , Fen F. Jamin , Gerhard Kunkel , Nirmal Chaudhary
发明人： Hua Shen , David Kotecki , Satish Athavale , Jenny Lian , Laertis Economikos , Fen F. Jamin , Gerhard Kunkel , Nirmal Chaudhary
IPC分类号： G03F700
CPC分类号： H01L21/7687 , H01L21/76885 , H01L27/10852 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the, electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.
摘要翻译：一种形成电极的方法。该方法包括通过第一电介质层形成导电插塞。插头从第一电介质层的上表面延伸到半导体衬底中的接触区域。光刻地形成电极，光刻中的掩模配准不对准，导致暴露屏障接触的表面部分。第二电介质层沉积在第一电介质层上，在形成的电极的侧面部分和顶部上方以及屏蔽接触的暴露部分之上。在设置在第一电介质层上的第二电介质层的部分上的第二电介质层的设置在电极的下侧的部分上以及在屏障接触的所述暴露部分上暴露第二电介质层的部分的牺牲材料在形成的电极的顶部和上侧部分上的介电层。第二介电层的暴露部分被去除，同时将第二介电层的部分留在屏障接触的暴露部分上。材料在氧化环境中沉积在第一电极的暴露部分和第二电介质层的剩余部分上。在材料上形成用于存储元件的第二电极。在形成电容器存储元件时，屏障接触部分的第二电介质层在材料形成过程中防止了屏障接触的氧化。

4. 发明授权

US06261967B1 Easy to remove hard mask layer for semiconductor device fabrication 有权
标题翻译：易于去除用于半导体器件制造的硬掩模层
公开(公告)号：US06261967B1
公开(公告)日：2001-07-17
申请号：US09501479
申请日：2000-02-09
申请人： Satish D. Athavale , Hua Shen , David Kotecki , Jenny Lian
发明人： Satish D. Athavale , Hua Shen , David Kotecki , Jenny Lian
IPC分类号： H01L21302
CPC分类号： H01L21/32136 , H01L21/0332 , H01L21/31116 , H01L21/32139 , H01L28/55 , H01L28/60
摘要： A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a dielectric layer and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains intact after the plasma etching and the hard mask removal.
摘要翻译：根据本发明的用于从贵金属形成图案形状的方法包括在电介质层上形成贵金属层并在贵金属层上图形化硬掩模层。硬掩模层包括可相对于贵金属层和电介质层选择性地移除并能耐受等离子体蚀刻的掩模材料。或者，在贵金属层等离子体蚀刻期间，硬掩模材料可能是可消耗的。根据图案化的硬掩模层在贵金属层上进行等离子体蚀刻。去除硬掩模层，使得在等离子体蚀刻和硬掩模去除之后，在贵金属层中形成的图案形状保持完整。

5. 发明申请

US20050196917A1 Method for forming a (111) oriented BSTO thin film layer for high dielectric constant capacitors 审中-公开
标题翻译：用于形成用于高介电常数电容器的（111）取向的BSTO薄膜层的方法
公开(公告)号：US20050196917A1
公开(公告)日：2005-09-08
申请号：US10790786
申请日：2004-03-03
申请人： Jingyu Lian , David Kotecki , Hua Shen , Robert Laibowitz , Katherine Saenger , Chenting Lin , Nicolas Nagel , Yunyu Wang , Satish Athavale , Thomas Shaw
发明人： Jingyu Lian , David Kotecki , Hua Shen , Robert Laibowitz , Katherine Saenger , Chenting Lin , Nicolas Nagel , Yunyu Wang , Satish Athavale , Thomas Shaw
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , H01L27/10852
摘要： A method for forming high capacitance crystalline dielectric layers with (111) texture is disclosed. In an exemplary embodiment, deposition of a plurality of nuclei is performed at a temperature in the range of about 430 to 460 degrees Celsius, followed by growth of a continuous BSTO dielectric layer at a temperature greater than 600 degrees Celsius. In an exemplary embodiment, a process is disclosed for growing a barium strontium titanium oxide film with high capacitance and thickness of about 30 nm or less.
摘要翻译：公开了一种形成具有（111）结构的高电容结晶介电层的方法。在一个示例性实施例中，多个核的沉积在约430至460摄氏度范围内的温度下进行，随后在大于600摄氏度的温度下生长连续的BSTO介电层。在示例性实施例中，公开了用于生长具有约30nm或更小的高电容和厚度的钡锶氧化钛膜的方法。

6. 发明授权

US06379577B2 Hydrogen peroxide and acid etchant for a wet etch process 失效
标题翻译：用于湿蚀刻工艺的过氧化氢和酸蚀刻剂
公开(公告)号：US06379577B2
公开(公告)日：2002-04-30
申请号：US09329894
申请日：1999-06-10
申请人： Hiroyuki Akatsu , David E. Kotecki , Jingyu Jenny Lian , Hua Shen
发明人： Hiroyuki Akatsu , David E. Kotecki , Jingyu Jenny Lian , Hua Shen
IPC分类号： H01L21302
CPC分类号： C04B41/009 , C04B41/5353 , C04B41/91 , C04B2111/00853 , H01L21/31111 , C04B35/465 , C04B35/472
摘要： A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO2.
摘要翻译：本文公开了用于选择性湿蚀刻设置在氧化硅或氮化硅衬底上的钛基钙钛矿材料的工艺和解决方案。溶液由过氧化氢，酸和去离子水组成。将溶液加热至25至90摄氏度之间的温度。钛基钙钛矿材料可以是钛酸锶钡，钛酸钡，钛酸锶或钛酸铅。该方案选择性地蚀刻钙钛矿材料，同时基板仅被最小蚀刻，如果有的话。该方法和解决方案允许对于包括SiO 2的各种衬底，阻挡层和掩模层选择性的类似钙钛矿材料，蚀刻速率高达常规蚀刻速率的三十倍。

7. 发明授权

US06420272B1 Method for removal of hard mask used to define noble metal electrode 失效
标题翻译：去除用于定义贵金属电极的硬掩模的方法
公开(公告)号：US06420272B1
公开(公告)日：2002-07-16
申请号：US09460700
申请日：1999-12-14
申请人： Hua Shen , David Edward Kotecki , Satish D. Athavale , Jenny Lian , Gerhard Kunkel , Nimal Chaudhary
发明人： Hua Shen , David Edward Kotecki , Satish D. Athavale , Jenny Lian , Gerhard Kunkel , Nimal Chaudhary
IPC分类号： H01L2100
CPC分类号： H01L28/60 , H01L21/02071 , H01L21/31116 , H01L21/32139 , H01L28/55
摘要： In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode. A method of removing the hard mask material without damaging the surrounding surface includes the steps of: depositing a soft mask photoresist material over the composite surface, including the hard masked covered noble metal electrode and the dielectric surface, in a manner such that the soft mask material is thinner over the region of the noble metal electrode; removing the portion of the soft mask material over the noble metal electrode leaving the soft mask material over the dielectric surface; etching the hard mask material with the soft mask material protecting the dielectric surface; and removing the remaining portion of the soft mask material.
摘要翻译：在使用高介电常数电介质材料形成的叠层电容器存储元件的半导体动态随机存取存储器电路中，典型的是使用贵金属电极形成叠层电容器。通常，贵金属电极的蚀刻工艺需要使用诸如氧化硅的硬掩模图形材料。去除这种硬掩模常常导致图案化的贵金属电极周围的电介质表面的损坏。在不损坏周围表面的情况下去除硬掩模材料的方法包括以下步骤：在复合表面上沉积软掩模光致抗蚀剂材料，包括硬掩蔽的贵金属电极和电介质表面，使得软掩模材料在贵金属电极的区域上较薄; 在所述贵金属电极上除去所述软掩模材料的所述部分，从而将所述软掩模材料留在所述电介质表面上; 用保护电介质表面的软掩模材料蚀刻硬掩模材料; 以及去除所述软掩模材料的剩余部分。

8. 发明授权

US06207584B1 High dielectric constant material deposition to achieve high capacitance 有权
标题翻译：高介电常数材料沉积实现高电容
公开(公告)号：US06207584B1
公开(公告)日：2001-03-27
申请号：US09478270
申请日：2000-01-05
申请人： Hua Shen , David E. Kotecki , Robert Laibowitz , Katherine Lynn Saenger , Satish D. Athavale , Jenny Lian , Martin Gutsche , Yun-Yu Wang , Thomas Shaw
发明人： Hua Shen , David E. Kotecki , Robert Laibowitz , Katherine Lynn Saenger , Satish D. Athavale , Jenny Lian , Martin Gutsche , Yun-Yu Wang , Thomas Shaw
IPC分类号： H01L2131
CPC分类号： H01L28/56 , H01L21/31691 , H01L28/90
摘要： A method for forming a dielectric layer includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.
摘要翻译：形成电介质层的方法包括在第一温度下将表面暴露于气态的第一电介质材料。在表面上形成第一介电材料的核。通过使用核作为种子用于层生长，在表面上沉积第二介电材料层，其中沉积在大于第一温度的第二温度下进行。

9. 发明授权

US06707086B1 Method for forming crystalline silicon nitride 失效
标题翻译：形成结晶氮化硅的方法
公开(公告)号：US06707086B1
公开(公告)日：2004-03-16
申请号：US09594638
申请日：2000-06-15
申请人： Rajarao Jammy , Philip L. Flaitz , Philip E. Batson , Hua Shen , Yun Yu Wang
发明人： Rajarao Jammy , Philip L. Flaitz , Philip E. Batson , Hua Shen , Yun Yu Wang
IPC分类号： H01L31119
CPC分类号： H01L21/28202 , C23C16/0218 , C23C16/345 , C23C16/56 , H01L21/3144 , H01L21/3185 , H01L27/10861 , H01L29/513 , H01L29/518 , H01L29/66181 , H01L29/945
摘要： In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed surface, precleaning the exposed surface by employing a hydrogen prebake and exposing the exposed surface to nitrogen to form a crystalline silicon nitride layer. Also, a trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surface substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the sidewalls of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.
摘要翻译：根据本发明，用于形成结晶氮化硅层的方法包括以下步骤：提供具有暴露表面的晶体硅衬底，通过使用氢预烘烤并将暴露表面暴露于氮以形成暴露表面，晶体氮化硅层。此外，根据本发明的沟槽电容器包括晶体硅衬底，其包括具有基本上不含天然氧化物的表面的深沟槽。在沟槽的侧壁上形成包括结晶氮化硅层的电介质叠层。电介质叠层在沟槽电容器的电极之间形成节点电介质。

10. 发明授权

US6057216A Low temperature diffusion process for dopant concentration enhancement 失效
标题翻译：掺杂剂浓度增强的低温扩散过程
公开(公告)号：US6057216A
公开(公告)日：2000-05-02
申请号：US987076
申请日：1997-12-09
申请人： Laertis Economikos , Cheruvu S. Murthy , Hua Shen
发明人： Laertis Economikos , Cheruvu S. Murthy , Hua Shen
IPC分类号： H01L21/225 , H01L21/334 , H01L21/822 , H01L23/00 , H01L27/04 , H01L29/94 , H01L21/38
CPC分类号： H01L29/66181 , H01L21/2255 , H01L29/945 , Y10S438/92
摘要： Doped semiconductor with high dopant concentrations in small semiconductor regions without excess spreading of the doped region are formed by:(a) applying a dopant-containing oxide glass layer on the semiconductor surface,(b) capping the dopant-containing oxide glass layer with a conformal silicon oxide layer,(c) heating the substrate from step (b) in a non-oxidizing atmosphere whereby at least a portion of the dopant in the glass diffuses into the substrate at the semiconductor surface, and(d) heating the glass-coated substrate from step (c) in an oxidizing atmosphere whereby at least a portion of the dopant in the glass near the semiconductor surface is forced into the substrate at the semiconductor surface by diffusion of oxygen through the glass.The method is especially useful for making buried plates in semiconductor substrates which may be used in trench capacitor structures. The preferred semiconductor substrate material is monocrystalline silicon. The preferred dopant is arsenic.
摘要翻译：通过：（a）在半导体表面上施加含掺杂剂的氧化物玻璃层，（b）用含有掺杂剂的氧化物玻璃层将掺杂剂氧化物玻璃层盖上（c）在非氧化气氛中加热来自步骤（b）的衬底，由此玻璃中的至少一部分掺杂剂在半导体表面扩散到衬底中，（d）加热玻璃 - 在步骤（c）中，在半导体表面附近的玻璃中的掺杂剂的至少一部分通过氧气扩散通过玻璃而被迫进入到半导体表面的衬底中。该方法对于将半导体衬底中的掩模板制成可用于沟槽电容器结构中是特别有用的。优选的半导体衬底材料是单晶硅。优选的掺杂剂是砷。

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