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1. 发明授权

US06207584B1 High dielectric constant material deposition to achieve high capacitance 有权
标题翻译：高介电常数材料沉积实现高电容
公开(公告)号：US06207584B1
公开(公告)日：2001-03-27
申请号：US09478270
申请日：2000-01-05
申请人： Hua Shen , David E. Kotecki , Robert Laibowitz , Katherine Lynn Saenger , Satish D. Athavale , Jenny Lian , Martin Gutsche , Yun-Yu Wang , Thomas Shaw
发明人： Hua Shen , David E. Kotecki , Robert Laibowitz , Katherine Lynn Saenger , Satish D. Athavale , Jenny Lian , Martin Gutsche , Yun-Yu Wang , Thomas Shaw
IPC分类号： H01L2131
CPC分类号： H01L28/56 , H01L21/31691 , H01L28/90
摘要： A method for forming a dielectric layer includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.
摘要翻译：形成电介质层的方法包括在第一温度下将表面暴露于气态的第一电介质材料。在表面上形成第一介电材料的核。通过使用核作为种子用于层生长，在表面上沉积第二介电材料层，其中沉积在大于第一温度的第二温度下进行。

2. 发明授权

US06339007B1 Capacitor stack structure and method of fabricating description 失效
标题翻译：电容器堆叠结构及其制造方法
公开(公告)号：US06339007B1
公开(公告)日：2002-01-15
申请号：US09562556
申请日：2000-05-02
申请人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
发明人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
IPC分类号： H01L2120
CPC分类号： H01L28/75 , H01L28/55 , H01L28/60
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.
摘要翻译：一种电容器结构，其包括顶部铂电极和在电极的侧壁上具有绝缘体的底部电极，并且其中底部电极从沉积相对于绝缘体在其侧壁上凹进的第一电极部分并且沉积第二绝缘体提供部分。

3. 发明授权

US06379577B2 Hydrogen peroxide and acid etchant for a wet etch process 失效
标题翻译：用于湿蚀刻工艺的过氧化氢和酸蚀刻剂
公开(公告)号：US06379577B2
公开(公告)日：2002-04-30
申请号：US09329894
申请日：1999-06-10
申请人： Hiroyuki Akatsu , David E. Kotecki , Jingyu Jenny Lian , Hua Shen
发明人： Hiroyuki Akatsu , David E. Kotecki , Jingyu Jenny Lian , Hua Shen
IPC分类号： H01L21302
CPC分类号： C04B41/009 , C04B41/5353 , C04B41/91 , C04B2111/00853 , H01L21/31111 , C04B35/465 , C04B35/472
摘要： A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO2.
摘要翻译：本文公开了用于选择性湿蚀刻设置在氧化硅或氮化硅衬底上的钛基钙钛矿材料的工艺和解决方案。溶液由过氧化氢，酸和去离子水组成。将溶液加热至25至90摄氏度之间的温度。钛基钙钛矿材料可以是钛酸锶钡，钛酸钡，钛酸锶或钛酸铅。该方案选择性地蚀刻钙钛矿材料，同时基板仅被最小蚀刻，如果有的话。该方法和解决方案允许对于包括SiO 2的各种衬底，阻挡层和掩模层选择性的类似钙钛矿材料，蚀刻速率高达常规蚀刻速率的三十倍。

4. 发明授权

US06178082B1 High temperature, conductive thin film diffusion barrier for ceramic/metal systems 失效
标题翻译：陶瓷/金属系统的高温导电薄膜扩散屏障
公开(公告)号：US06178082B1
公开(公告)日：2001-01-23
申请号：US09031236
申请日：1998-02-26
申请人： Mukta S. Farooq , David E. Kotecki , Robert A. Rita , Stephen M. Rossnagel
发明人： Mukta S. Farooq , David E. Kotecki , Robert A. Rita , Stephen M. Rossnagel
IPC分类号： H01G4005
CPC分类号： H01L23/49894 , H01L21/28568 , H01L23/49827 , H01L23/49866 , H01L28/75 , H01L2224/16 , H01L2924/01019 , H01L2924/01046 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/15311 , H01L2924/19103 , H05K1/0306 , H05K1/162
摘要： A multilayer ceramic substrate having a thin film structure containing capacitor connected thereto is provided as an interposer capacitor, the capacitor employing platinum as the bottom electrode of the capacitor. In a preferred capacitor, a dielectric material such as barium titanate is used as the dielectric material between the capacitor electrodes. The fabrication of the interposer capacitor requires an in-situ or post deposition high temperature anneal and the use of such dielectrics requires heating of the capacitor structure in a non-reducing atmosphere. A layer of a high temperature, thin film diffusion barrier such as TaSiN on the lower platinum electrode between the electrode and underlying multilayer ceramic substrate prevents or minimizes oxidization of the metallization of the multilayer ceramic substrate to which the thin film structure is connected during the fabrication process. A method is also provided for fabricating an interposer capacitor with a multilayer ceramic substrate base and a thin film multilayer structure having at least one capacitor comprising at least one bottom platinum electrode.
摘要翻译：提供具有包含与其连接的电容器的薄膜结构的多层陶瓷基板作为插入电容器，该电容器采用铂作为电容器的底部电极。在优选的电容器中，使用诸如钛酸钡的电介质材料作为电容器电极之间的电介质材料。中间层电容器的制造需要原位或后沉积高温退火，并且使用这种电介质需要在非还原气氛中加热电容器结构。在电极和下面的多层陶瓷基板之间的下铂电极上的诸如TaSiN的高温薄膜扩散阻挡层的层防止或最小化在制造期间薄膜结构连接到的多层陶瓷基板的金属化的氧化处理。还提供了一种用于制造具有多层陶瓷衬底基底和具有至少一个包括至少一个底部铂电极的电容器的薄膜多层结构的插入式电容器的方法。

5. 发明授权

US6124199A Method for simultaneously forming a storage-capacitor electrode and interconnect 失效
标题翻译：同时形成储存电容电极和互连的方法
公开(公告)号：US6124199A
公开(公告)日：2000-09-26
申请号：US300900
申请日：1999-04-28
申请人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
发明人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
IPC分类号： H01L21/02 , H01L21/8242 , H01L23/522 , H01H21/4763
CPC分类号： H01L27/10885 , H01L23/522 , H01L27/10894 , H01L28/55 , H01L2924/0002
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括与存储电容器的各个板同时形成的下电容器电极和上电容器电极。两个电容器电极可用于在DRAM单元阵列内形成不同的互连。

6. 发明授权

US6010748A Method of delivering source reagent vapor mixtures for chemical vapor deposition using interiorly partitioned injector 失效
标题翻译：使用内部分隔的注射器输送用于化学气相沉积的源试剂蒸汽混合物的方法
公开(公告)号：US6010748A
公开(公告)日：2000-01-04
申请号：US17384
申请日：1998-02-03
申请人： Peter C. Van Buskirk , James A. Fair , David E. Kotecki
发明人： Peter C. Van Buskirk , James A. Fair , David E. Kotecki
IPC分类号： C23C16/44 , C23C16/455 , C23C16/40
CPC分类号： C23C16/45565 , C23C16/455
摘要： A showerhead disperser device for mixing plural vapor streams, comprising: a housing including front and rear walls in spaced apart relation to one another, and a side wall therebetween, defining within the housing an interior volume; the front wall having a multiplicity of vapor mixture discharge openings therein, for discharging mixed vapor from the interior volume of the housing exteriorly thereof, flow passages joined to the housing for introducing into the interior volume of the housing respective fluids to be mixed therein; and at least one baffle plate mounted in the interior volume of the housing, intermediate the front and rear walls of the housing, the baffle plate having an edge in spaced relation to the side wall to form an annular flow passage therebetween and the baffle plate having at least one of the respective fluids directed thereagainst upon introduction to the interior volume of the housing, for distribution thereof in the interior volume of the housing. The baffled showerhead disperser is usefully employed to enable formation of CVD thin films of highly uniform composition and thickness.
摘要翻译：一种用于混合多个蒸汽流的喷头分散装置，包括：壳体，其包括彼此间隔开的前壁和后壁以及其间的侧壁，在所述壳体内限定内部容积; 所述前壁在其中具有多个蒸汽混合物排出口，用于从其外部的所述壳体的内部容积排出混合蒸气，流动通道连接到所述壳体，以将待混合的各种流体引入到所述壳体的内部容积中; 以及安装在所述壳体的内部容积中的至少一个挡板，位于所述壳体的前壁和后壁之间，所述挡板具有与所述侧壁间隔开的边缘，以在其间形成环形流动通道，并且所述挡板具有各个流体中的至少一个在引入壳体的内部空间时被引导到其上，以将其分配在壳体的内部空间中。挡板式喷头分散机有利地用于形成高度均匀组成和厚度的CVD薄膜。

7. 发明授权

US5268069A Safe method for etching silicon dioxide 失效
标题翻译：蚀刻二氧化硅的安全方法
公开(公告)号：US5268069A
公开(公告)日：1993-12-07
申请号：US895493
申请日：1992-06-08
申请人： Jonathan D. Chapple-Sokol , Richard A. Conti , David E. Kotecki , Andrew H. Simon , Manu Tejwani
发明人： Jonathan D. Chapple-Sokol , Richard A. Conti , David E. Kotecki , Andrew H. Simon , Manu Tejwani
IPC分类号： H01L21/306 , H01L21/311 , H01L21/00
CPC分类号： H01L21/02046 , H01L21/02049 , H01L21/31116
摘要： Anhydrous ammonium fluoride is used as a safe source of hydrogen fluoride for etching native or other silicon dioxide layers from silicon substrates. Heating the anhydrous ammonium fluoride above its sublimation temperature results in the generation of hydrogen fluoride gas which etches the silicon dioxide. Controlled amounts of water vapor are used during the etch reaction to ensure complete etching of the thin oxide layers down to within hundredths of a monolayer and to achieve precise etch rate control.
摘要翻译：无水氟化铵用作氟化氢的安全源，用于从硅衬底蚀刻天然或其他二氧化硅层。在其升华温度以上加热无水氟化铵导致产生二氧化硅蚀刻的氟化氢气体。在蚀刻反应期间使用受控量的水蒸气，以确保将薄氧化物层完全蚀刻到百分之几以下的单层并且实现精确的蚀刻速率控制。

8. 发明授权

US5134963A LPCVD reactor for high efficiency, high uniformity deposition 失效
标题翻译： LPCVD反应器用于高效率，高均匀性沉积
公开(公告)号：US5134963A
公开(公告)日：1992-08-04
申请号：US784160
申请日：1991-10-28
申请人： Steven G. Barbee , Jonathan D. Chapple-Sokol , Richard A. Conti , David E. Kotecki
发明人： Steven G. Barbee , Jonathan D. Chapple-Sokol , Richard A. Conti , David E. Kotecki
IPC分类号： C23C16/52 , C23C16/44 , C23C16/455 , C30B25/14 , H01L21/205
CPC分类号： C23C16/45565 , C23C16/455 , C23C16/45504 , C30B25/14
摘要： An injector with a convex wall surface facing the susceptor directs vapor toward a wafer held by a susceptor producing a generally laminar flow across the surface of the wafer that in combination with the convex wall surface prevents formation of recirculation cells in the region between the wafer and the injector.

9. 发明授权

US06429474B1 Storage-capacitor electrode and interconnect 失效
标题翻译：储存电容电极和互连
公开(公告)号：US06429474B1
公开(公告)日：2002-08-06
申请号：US09547335
申请日：2000-04-11
申请人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
发明人： Jeffrey P. Gambino , Gary B. Bronner , David E. Kotecki , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L23/522 , H01L27/10894 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括与存储电容器的各个板同时形成的下电容器电极和上电容器电极。两个电容器电极可用于在DRAM单元阵列内形成不同的互连。

10. 发明授权

US06395594B2 Method for simultaneously forming a storage-capacitor electrode and interconnect 失效
标题翻译：同时形成储存电容电极和互连的方法
公开(公告)号：US06395594B2
公开(公告)日：2002-05-28
申请号：US09750790
申请日：2001-01-02
申请人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
发明人： David E. Kotecki , Carl J. Radens , Jeffrey P. Gambino , Gary B. Bronner
IPC分类号： H01L218234
CPC分类号： H01L27/10882 , H01L27/10894
摘要： A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.
摘要翻译： DRAM存储单元阵列包括在单元的存储电容器级形成的布线层，用于建立互补位线的翻转连接，或用于连接DRAM单元阵列中的支持电路。布线层包括用于制造两种类型互连的至少一个并且优选两个电容器电极。制造DRAM存储单元的方法包括：形成一个或多个电容电极，同时形成存储单元的存储电容器的电极，以及与辅助电容器电极相同的材料。

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