专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09070759B2 Semiconductor device and method of making same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09070759B2
公开(公告)日：2015-06-30
申请号：US11526499
申请日：2006-09-25
申请人： Jin-Ping Han , Haoren Zhuang , Jiang Yan , Jingyu Lian , Manfred Eller
发明人： Jin-Ping Han , Haoren Zhuang , Jiang Yan , Jingyu Lian , Manfred Eller
IPC分类号： H01L21/336 , H01L21/311 , H01L29/51 , H01L29/78 , H01L29/423 , H01L21/28 , H01L29/49 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/28017 , H01L21/28123 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/82385 , H01L29/42364 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/66575 , H01L29/66636 , H01L29/78
摘要： A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.
摘要翻译：公开了制造半导体器件的方法。器件制造在半导体主体上。栅电极设置在半导体本体上，在栅电极和半导体本体之间具有栅极电介质，其中栅极电介质具有大于栅电极的长度。第一源极/漏极区域设置在与栅极的第一边缘相邻的半导体本体内，栅极电介质至少部分地与第一源极/漏极区域重叠，并且第二源极/漏极区域设置在与半导体本体相邻的第二源极/漏极区域内具有栅极电介质的栅极的第一边缘至少部分地与第二源极/漏极区重叠。

2. 发明申请

US20080176344A1 Feature Dimension Control in a Manufacturing Process 有权
标题翻译：制造过程中的特征尺寸控制
公开(公告)号：US20080176344A1
公开(公告)日：2008-07-24
申请号：US11625575
申请日：2007-01-22
申请人： Haoren Zhuang , Alois Gutmann , Matthias Lipinski , Chandrasekhar Sarma , Jingyu Lian
发明人： Haoren Zhuang , Alois Gutmann , Matthias Lipinski , Chandrasekhar Sarma , Jingyu Lian
IPC分类号： H01L21/66 , C23F1/00
CPC分类号： H01L21/32137 , H01L22/12
摘要： A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.
摘要翻译：公开了一种用于制造半导体器件的方法，其包括确定设置在工件上的材料层中的图案的尺寸或其他物理特性，以及使用与所述尺寸相关的信息来蚀刻所述材料层。还公开了一种用于制造半导体器件的系统，该半导体器件包括被配置为蚀刻层以限定该层中的图案的第一蚀刻系统，以及被配置为测量该图案的物理特性的第二蚀刻系统，基于物理特性，并根据蚀刻控制参数刻蚀该层。

3. 发明申请

US20080044741A1 Metrology systems and methods for lithography processes 有权
标题翻译：用于光刻工艺的计量系统和方法
公开(公告)号：US20080044741A1
公开(公告)日：2008-02-21
申请号：US11504388
申请日：2006-08-15
申请人： Chandrasekhar Sarma , Jingyu Lian , Matthias Lipinski , Haoren Zhuang
发明人： Chandrasekhar Sarma , Jingyu Lian , Matthias Lipinski , Haoren Zhuang
IPC分类号： G03F1/00 , G06F17/50 , G03C5/00 , G03B27/42
CPC分类号： G03F7/70425 , G03F7/70483
摘要： Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.
摘要翻译：公开了用于光刻工艺的计量系统和方法。在一个实施例中，制造半导体器件的方法包括提供具有形成在其上的多个圆角圆形测试图案的掩模。提供第一半导体器件，并且使用掩模和光刻工艺，利用多个拐角圆形测试特征对第一半导体器件的感光材料层进行构图。通过分析相对于形成在半导体器件的感光材料层上的多个角圆切削测试特征中的其它角点的多个角圆测试特征来测量光刻工艺的角圆角。光刻处理或掩模响应于测量的角圆度的量而改变，并且提供第二半导体器件。使用改变的光刻工艺或改变的掩模影响第二半导体器件。

4. 发明授权

US07270884B2 Adhesion layer for Pt on SiO2 有权
标题翻译： Pt上的粘附层
公开(公告)号：US07270884B2
公开(公告)日：2007-09-18
申请号：US10408339
申请日：2003-04-07
申请人： Jingyu Lian , Kwong Hon Wong , Michael Wise , Young Limb , Nicolas Nagel
发明人： Jingyu Lian , Kwong Hon Wong , Michael Wise , Young Limb , Nicolas Nagel
IPC分类号： B32B9/06
CPC分类号： H01L28/65 , Y10T428/12597 , Y10T428/12875
摘要： Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO2) substrate in capacitor structures of memory devices.
摘要翻译：使用Si，Al，Al，TiN和IrO 2作为粘合层，以防止诸如Pt的贵金属电极从存储器件的电容器结构中的二氧化硅（SiO 2）衬底剥离。

5. 发明授权

US07061035B2 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US07061035B2
公开(公告)日：2006-06-13
申请号：US10677852
申请日：2003-10-01
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬垫层，并且蚀刻用于VO触点的孔，直到蚀刻被衬垫层停止。

6. 发明申请

US20050196917A1 Method for forming a (111) oriented BSTO thin film layer for high dielectric constant capacitors 审中-公开
标题翻译：用于形成用于高介电常数电容器的（111）取向的BSTO薄膜层的方法
公开(公告)号：US20050196917A1
公开(公告)日：2005-09-08
申请号：US10790786
申请日：2004-03-03
申请人： Jingyu Lian , David Kotecki , Hua Shen , Robert Laibowitz , Katherine Saenger , Chenting Lin , Nicolas Nagel , Yunyu Wang , Satish Athavale , Thomas Shaw
发明人： Jingyu Lian , David Kotecki , Hua Shen , Robert Laibowitz , Katherine Saenger , Chenting Lin , Nicolas Nagel , Yunyu Wang , Satish Athavale , Thomas Shaw
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , H01L27/10852
摘要： A method for forming high capacitance crystalline dielectric layers with (111) texture is disclosed. In an exemplary embodiment, deposition of a plurality of nuclei is performed at a temperature in the range of about 430 to 460 degrees Celsius, followed by growth of a continuous BSTO dielectric layer at a temperature greater than 600 degrees Celsius. In an exemplary embodiment, a process is disclosed for growing a barium strontium titanium oxide film with high capacitance and thickness of about 30 nm or less.
摘要翻译：公开了一种形成具有（111）结构的高电容结晶介电层的方法。在一个示例性实施例中，多个核的沉积在约430至460摄氏度范围内的温度下进行，随后在大于600摄氏度的温度下生长连续的BSTO介电层。在示例性实施例中，公开了用于生长具有约30nm或更小的高电容和厚度的钡锶氧化钛膜的方法。

7. 发明授权

US06839220B1 Multi-layer barrier allowing recovery anneal for ferroelectric capacitors 有权
标题翻译：用于铁电电容器的多层屏障允许恢复退火
公开(公告)号：US06839220B1
公开(公告)日：2005-01-04
申请号：US10623461
申请日：2003-07-18
申请人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
发明人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
IPC分类号： H01G4/06 , H01G4/12 , H01G4/33 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。外扩散阻挡层覆盖电容器的铁电体。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

8. 发明授权

US08138055B2 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same 有权
标题翻译：具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US08138055B2
公开(公告)日：2012-03-20
申请号：US12850119
申请日：2010-08-04
申请人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
发明人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
摘要翻译：在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

9. 发明授权

US07745292B2 Method for fabricating a semiconductor gate structure 有权
标题翻译：半导体栅极结构的制造方法
公开(公告)号：US07745292B2
公开(公告)日：2010-06-29
申请号：US11872298
申请日：2007-10-15
申请人： Jingyu Lian , Jong Pyo Kim
发明人： Jingyu Lian , Jong Pyo Kim
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/26506 , H01L21/823835 , H01L29/665
摘要： A method of making a semiconductor device is disclosed. A mask if formed over a first and a second region of a semiconductor body, and a vertical diffusion barrier is formed in a region between the first and second regions. A mask is then formed over the second region and the first region is left unmasked. The semiconductor body is exposed to a dopant, so that the first region is doped and the second region is blocked from the dopant by the mask and by the vertical diffusion barrier.
摘要翻译：公开了制造半导体器件的方法。如果形成在半导体主体的第一和第二区域上的掩模，并且在第一和第二区域之间的区域中形成垂直扩散阻挡层。然后在第二区域上形成掩模，并且第一区域未被掩蔽。半导体本体暴露于掺杂剂，使得第一区域被掺杂，并且第二区域被掩模和垂直扩散阻挡层阻挡掺杂剂。

10. 发明申请

US20100120177A1 Feature Dimension Control in a Manufacturing Process 审中-公开
标题翻译：制造过程中的特征尺寸控制
公开(公告)号：US20100120177A1
公开(公告)日：2010-05-13
申请号：US12691218
申请日：2010-01-21
申请人： Haoren Zhuang , Alois Gutmann , Matthias Lipinski , Chandrasekhar Sarma , Jingyu Lian
发明人： Haoren Zhuang , Alois Gutmann , Matthias Lipinski , Chandrasekhar Sarma , Jingyu Lian
IPC分类号： H01L21/66 , H01L21/3065 , H01L21/308 , H01L21/306
CPC分类号： H01L21/32137 , H01L22/12
摘要： A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.
摘要翻译：公开了一种用于制造半导体器件的方法，其包括确定设置在工件上的材料层中的图案的尺寸或其他物理特性，以及使用与所述尺寸相关的信息来蚀刻所述材料层。还公开了一种用于制造半导体器件的系统，该半导体器件包括被配置为蚀刻层以限定该层中的图案的第一蚀刻系统，以及被配置为测量该图案的物理特性的第二蚀刻系统，基于物理特性，并根据蚀刻控制参数刻蚀该层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式