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1. 发明授权

US06958506B2 High-dielectric constant insulators for feol capacitors 有权
标题翻译：高介电常数绝缘子
公开(公告)号：US06958506B2
公开(公告)日：2005-10-25
申请号：US10688508
申请日：2003-10-17
申请人： Evgeni P. Gousev , Harald F. Okorn-Schmidt , Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh
发明人： Evgeni P. Gousev , Harald F. Okorn-Schmidt , Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh
IPC分类号： H01L29/73 , H01L21/02 , H01L21/28 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L21/8234 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/08 , H01L29/51 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L27/0629 , H01L27/0635 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.
摘要翻译：提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器结构体。本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

2. 发明授权

US06667207B2 High-dielectric constant insulators for FEOL capacitors 失效
标题翻译：用于FEOL电容器的高介电常数绝缘子
公开(公告)号：US06667207B2
公开(公告)日：2003-12-23
申请号：US10246110
申请日：2002-09-18
申请人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
发明人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
IPC分类号： H01L218249
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L27/0629 , H01L27/0635 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.
摘要翻译：提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器结构体。本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。

3. 发明授权

US06511873B2 High-dielectric constant insulators for FEOL capacitors 有权
公开(公告)号：US06511873B2
公开(公告)日：2003-01-28
申请号：US09882749
申请日：2001-06-15
申请人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
发明人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Douglas D. Coolbaugh , Evgeni P. Gousev , Harald F. Okorn-Schmidt
IPC分类号： H01L2100
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L27/0629 , H01L27/0635 , H01L27/0805 , H01L28/55 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

4. 发明授权

US06444592B1 Interfacial oxidation process for high-k gate dielectric process integration 有权
标题翻译：用于高k栅介质工艺集成的界面氧化工艺
公开(公告)号：US06444592B1
公开(公告)日：2002-09-03
申请号：US09597765
申请日：2000-06-20
申请人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Matthew W. Copel , Christopher P. D'Emic , Evgeni P. Gousev , Fenton Read McFeely , Joseph S. Newbury , Harald F. Okorn-Schmidt , Patrick R. Varekamp , Theodore H. Zabel
发明人： Arne W. Ballantine , Douglas A. Buchanan , Eduard A. Cartier , Kevin K. Chan , Matthew W. Copel , Christopher P. D'Emic , Evgeni P. Gousev , Fenton Read McFeely , Joseph S. Newbury , Harald F. Okorn-Schmidt , Patrick R. Varekamp , Theodore H. Zabel
IPC分类号： H01L21469
CPC分类号： H01L21/31691 , H01L28/56
摘要： A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.
摘要翻译：提供了一种将高k材料集成到CMOS处理方案中的方法。该方法包括在半导体衬底的器件区域上形成界面氧化物，氧氮化物和/或氮化物层，所述界面层的厚度小于10埃; 和（b）在所述界面氧化物，氧氮化物和/或氮化物层上形成高k电介质材料，所述高k电介质的介电常数k大于8。

5. 发明授权

US06346487B1 Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer 失效
标题翻译：在半导体晶片上形成氧氮化物绝缘层的装置和方法
公开(公告)号：US06346487B1
公开(公告)日：2002-02-12
申请号：US09803503
申请日：2001-03-10
申请人： Douglas A. Buchanan , Evgeni P. Gousev , Carol J. Heenan , Wade J. Hodge , Steven M. Shank , Patrick R. Varekamp
发明人： Douglas A. Buchanan , Evgeni P. Gousev , Carol J. Heenan , Wade J. Hodge , Steven M. Shank , Patrick R. Varekamp
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C23C16/308 , C23C16/401 , C23C16/452 , C23C16/453 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L21/3115 , H01L21/3144 , H01L29/518
摘要： An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube. Gas injection orifices on the order of several millimeters then distribute the pre-decomposed gas to the wafers, producing a more uniformly N-doped wafer load in a batch furnace.
摘要翻译：一种在基板上形成氧氮化物绝缘层的装置和方法，其通过将基板置于炉的主室内的第一温度下，在高于第一温度的第二温度下将基板暴露于含氮气体，并在存在后燃烧气体的情况下在主室内的衬底上生长氧氮化物层。较高温度的含氮气体在主室外的室内燃烧。较高的温度在800至1200℃的范围内，优选950℃。在第二实施例中，主室内的分布式N2O气体喷射器输送含氮气体。含氮气体在室外预加热。然后将含氮气体输送到气体歧管，气体歧管分裂气体流并将气体引导到主处理管内的多个气体喷射器，优选两至四个喷射器。大约数毫米的气体注入孔然后将预分解的气体分配到晶片，在间歇炉中产生更均匀的N掺杂晶片负载。

6. 发明授权

US07326610B2 Process options of forming silicided metal gates for advanced CMOS devices 有权
标题翻译：为先进的CMOS器件形成硅化金属栅的工艺选择
公开(公告)号：US07326610B2
公开(公告)日：2008-02-05
申请号：US11271032
申请日：2005-11-10
申请人： Ricky S. Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Evgeni P. Gousev , Victor Ku , An Steegen
发明人： Ricky S. Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Evgeni P. Gousev , Victor Ku , An Steegen
IPC分类号： H01L21/31
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823835
摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要翻译：硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或现有的金属门。硅化物用作连接CMOS结构的PFET和NFET器件的选项。该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。提供了具有栅极和源极和漏极区域的半导体衬底。栅极电介质层与金属栅极层一起沉积在衬底上。然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。可以在栅极内使用第二硅化物。在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

7. 发明授权

US07029966B2 Process options of forming silicided metal gates for advanced CMOS devices 失效
标题翻译：为先进的CMOS器件形成硅化金属栅的工艺选择
公开(公告)号：US07029966B2
公开(公告)日：2006-04-18
申请号：US10605261
申请日：2003-09-18
申请人： Ricky S. Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Evgeni P. Gousev , Victor Ku , An Steegen
发明人： Ricky S. Amos , Douglas A. Buchanan , Cyril Cabral, Jr. , Evgeni P. Gousev , Victor Ku , An Steegen
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/76895 , H01L21/823835
摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要翻译：硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或现有的金属门。硅化物用作连接CMOS结构的PFET和NFET器件的选项。该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。提供了具有栅极和源极和漏极区域的半导体衬底。栅极电介质层与金属栅极层一起沉积在衬底上。然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。可以在栅极内使用第二硅化物。在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

8. 发明授权

US06436196B1 Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer 失效
公开(公告)号：US06436196B1
公开(公告)日：2002-08-20
申请号：US09887505
申请日：2001-06-22
申请人： Douglas A. Buchanan , Evgeni P. Gousev , Carol J. Heenan , Wade J. Hodge , Steven M. Shank , Patrick R. Varekamp
发明人： Douglas A. Buchanan , Evgeni P. Gousev , Carol J. Heenan , Wade J. Hodge , Steven M. Shank , Patrick R. Varekamp
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C23C16/308 , C23C16/401 , C23C16/452 , C23C16/453 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L21/3115 , H01L21/3144 , H01L29/518
摘要： An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube. Gas injection orifices on the order of several millimeters then distribute the pre-decomposed gas to the wafers, producing a more uniformly N-doped wafer load in a batch furnace.

9. 发明授权

US06887797B2 Apparatus and method for forming an oxynitride insulating layer on a semiconductor wafer 失效
标题翻译：在半导体晶片上形成氧氮化物绝缘层的装置和方法
公开(公告)号：US06887797B2
公开(公告)日：2005-05-03
申请号：US10199542
申请日：2002-07-19
申请人： Douglas A. Buchanan , Evgeni P. Gousev , Carol J. Heenan , Wade J. Hodge , Steven M. Shank , Patrick R. Varekamp
发明人： Douglas A. Buchanan , Evgeni P. Gousev , Carol J. Heenan , Wade J. Hodge , Steven M. Shank , Patrick R. Varekamp
IPC分类号： C23C16/30 , C23C16/40 , C23C16/452 , C23C16/453 , H01L21/28 , H01L21/3115 , H01L21/314 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28185 , C23C16/308 , C23C16/401 , C23C16/452 , C23C16/453 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L21/3115 , H01L21/3144 , H01L29/518
摘要： An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube. Gas injection orifices on the order of several millimeters then distribute the pre-decomposed gas to the wafers, producing a more uniformly N-doped wafer load in a batch furnace.
摘要翻译：一种在基板上形成氧氮化物绝缘层的装置和方法，其通过将基板放置在炉的主室内的第一温度下，在高于第一温度的第二温度下将基板暴露于含氮气体，并在存在后燃烧气体的情况下在主室内的衬底上生长氧氮化物层。较高温度的含氮气体在主室外的室内燃烧。较高的温度在800至1200℃的范围内，优选950℃。在第二实施例中，主室内的分布式N 2 O气体喷射器输送含氮气体。含氮气体在室外预加热。然后将含氮气体输送到气体歧管，气体歧管分裂气体流并将气体引导到主处理管内的多个气体喷射器，优选两至四个喷射器。大约数毫米的气体注入孔然后将预分解的气体分配到晶片，在间歇炉中产生更均匀的N掺杂晶片负载。

10. 发明授权

US07887711B2 Method for etching chemically inert metal oxides 有权
标题翻译：蚀刻化学惰性金属氧化物的方法
公开(公告)号：US07887711B2
公开(公告)日：2011-02-15
申请号：US10170914
申请日：2002-06-13
申请人： Douglas A. Buchanan , Eduard A. Cartier , Evgeni Gousev , Harald Okorn-Schmidt , Katherine L. Saenger
发明人： Douglas A. Buchanan , Eduard A. Cartier , Evgeni Gousev , Harald Okorn-Schmidt , Katherine L. Saenger
IPC分类号： B44C1/22 , H01L21/00
CPC分类号： H01L21/31122 , Y10S438/924
摘要： A system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an energetic particle bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. Besides using the ion implantation damage (I/I damage) plus wet etch technique to metal oxides (including metal oxides not previously etchable by wet methods), other damage methods including lower energy, plasma-based ion bombardment, may be implemented. Plasma-based ion bombardment typically uses simpler and cheaper tooling, and results in less collateral damage to underlying structures as the damage profile can be more easily localized to the depth of the thin metal oxide film.
摘要翻译：一种在半导体结构中图案化金属氧化物材料的系统和方法。该方法包括在衬底上沉积金属氧化物材料层的第一步骤。然后，在金属氧化物层之上形成图案化掩模层，留下暴露金属氧化物层的一个或多个第一区域。接着对金属氧化物层的暴露的第一区域进行高能粒子轰击处理，从而破坏金属氧化物层的第一区域。然后通过化学蚀刻去除金属氧化物层的暴露和损坏的第一区域。有利地，该系统和方法被实现以在小规模半导体器件中提供高k电介质材料。除了使用离子注入损伤（I / I损伤）以及湿法蚀刻技术对金属氧化物（包括以前不能用湿法蚀刻的金属氧化物）外，还可以实施包括较低能量，基于等离子体的离子轰击等其他损伤方法。基于等离子体的离子轰击通常使用更简单和更便宜的工具，并且导致对下面的结构的较少的附带损伤，因为损伤分布可以更容易地定位于薄金属氧化物膜的深度。

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